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PDF M59BW10225N1T Data sheet ( Hoja de datos )
| Número de pieza | M59BW10225N1T | |
| Descripción | 1 Mbit 64Kb x16 / Burst Low Voltage Flash Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M59BW102
1 Mbit (64Kb x16, Burst) Low Voltage Flash Memory
PRELIMINARY DATA
s 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
s SEQUENTIAL CYCLE TIME: 25ns
s RANDOM ACCESS TIME
s PROGRAMMING TIME: 10µs typical
s INTERLEAVED ACCESS TIME: 16ns
s CONTINUOUS MEMORY INTERLEAVING
– Unlimited Linear Access Data Output
s PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Word-by-Word
– Status Register bits
s LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
s 100,000 PROGRAM/ERASE CYCLES
s 20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: C1h
DESCRIPTION
The M59BW102 is a non-volatile memory that may
be erased electrically at the chip level and pro-
grammed in-system on a Word-by-Word basis us-
ing only a single 3V VCC supply. For Program and
Erase operations the necessary high voltages are
generated internally. The device can also be pro-
grammed in standard programmers.
The device can be programmed and erased over
100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature, Programming and
Chip Erase are written to the device in cycles of
commands to a Command Interface using stan-
dard microprocessor write timings. The
M59BW102 features an interleaved access mo-
dality which allows extremely fast access time.
The device is offered in TSOP40 (10 x 14mm)
package.
TSOP40 (N)
10 x 14mm
Figure 1. Logic Diagram
VCC
16
A0-A15
16
DQ0-DQ15
W
E M59BW102
G
ALE
VSS
AI02763B
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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1 page  
Figure 3. Non Linear and Linear Access Cycle Timing Diagram
M59BW102
5/24
5 Page 
M59BW102
Table 13. Random Read Mode AC Characteristics
(TA = 0 to 70°C)
M59BW102
Symbol Alt
Parameter
Test Condition
25
VCC = 3.0V to 3.6V
Min Typ Max
tALHALL
tALW
Address Latch Enable High to Address
Latch Enable Low
ALE = Pulse
10
tELALL
tE
Chip Enable Low to Address Latch Enable
Low
10
tAXALL
tAS
Address Transition to Address Latch
Enable Low
6
tEHALH
tELV
Chip Enable High to Address Latch Enable
High
3
tALLGL
tAG
Address Latch Enable Low to Output
Enable Low
7.5
tGHALH
tQP
Output Enable High to Address Latch
Enable High
0
tGHGL tGW Output Enable High to Output Enable Low
G = Pulse
14
tGLGH
tGL Output Enable Low to Output Enable High
48
tGLQV (1) tGACC Output Enable Low to Output Valid
30
tELQV (1) tEACC Chip Enable Low to Output Valid
55
tGHEL
tGE Output Enable High to Chip Enable Low
–2
tEHQZ tEDF Chip Enable High to Output Hi-Z
12
tALHQZ tADF Address Latch Enable High to Output Hi-Z
20
tQVGH
tQV Output Valid to Output Enable High
10
tGHEH
tGE Output Enable High to Chip Enable High
0
tELGL
tEGL Chip Enable Low to Output Enable Low
13
tEHQV
Chip Enable High to Data Hold
0
tALLAX
Address Latch Enable Low to Address
Transition
30
Note: 1. This timing refers to a Load Capacitance (CL) of 30pF. If CL is higher, add 1ns for each extra 10pF.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet M59BW10225N1T.PDF ] | |
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