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PDF M58LW032A90N6T Data sheet ( Hoja de datos )
| Número de pieza | M58LW032A90N6T | |
| Descripción | 32 Mbit 2Mb x16 / Uniform Block / Burst 3V Supply Flash Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M58LW032A
32 Mbit (2Mb x16, Uniform Block, Burst)
3V Supply Flash Memory
FEATURES SUMMARY
s WIDE x16 DATA BUS for HIGH BANDWIDTH
s SUPPLY VOLTAGE
– VDD = 2.7 to 3.6V core supply voltage for Pro-
gram, Erase and Read operations
– VDDQ = 1.8V to VDD for I/O Buffers
s SYNCHRONOUS/ASYNCHRONOUS READ
– Synchronous Burst read
– Asynchronous Random Read
– Asynchronous Address Latch Controlled
Read
– Page Read
s ACCESS TIME
– Synchronous Burst Read up to 56MHz
– Asynchronous Page Mode Read 90/25ns and
110/25ns
– Random Read 90ns, 110ns.
s PROGRAMMING TIME
– 16 Word Write Buffer
– 18µs Word effective programming time
s 64 UNIFORM 32 KWord MEMORY BLOCKS
s BLOCK PROTECTION/ UNPROTECTION
s PROGRAM and ERASE SUSPEND
s 128 bit PROTECTION REGISTER
s COMMON FLASH INTERFACE
s 100, 000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code M58LW032A: 8816h
Figure 1. Packages
TSOP56 (N)
14 x 20 mm
TBGA
TBGA64 (ZA)
10 x 13 mm
February 2003
1/61
1 page  
M58LW032A
Figure 24. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 51
Figure 25. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 53
Figure 27. Block Protect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 28. Blocks Unprotect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 29. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 56
Figure 30. Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . 57
Figure 31. Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . 58
Figure 32. Command Interface and Program Erase Controller Flowchart (c). . . . . . . . . . . . . . . . 59
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 32. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5/61
5 Page 
M58LW032A
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A1-A21). The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
Chip Enable and Latch Enable must be low when
selecting the addresses.
The address inputs are latched on the rising edge
of Chip Enable, Write Enable or Latch Enable,
whichever occurs first in a Write operation. The
address latch is transparent when Latch Enable is
low, VIL. The address is internally latched in an
Erase or Program operation.
Data Inputs/Outputs (DQ0-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
When Chip Enable and Output Enable are both
low, VIL, the data bus outputs data from the mem-
ory array, the Electronic Signature, the Block Pro-
tection status, the CFI Information or the contents
of the Status Register. The data bus is high imped-
ance when the chip is deselected, Output Enable
is high, VIH, or the Reset/Power-Down signal is
low, VIL. When the Program/Erase Controller is
active the Ready/Busy status is given on DQ7.
Chip Enable (E). The Chip Enable, E, input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. Chip Enable, E, at
VIH deselects the memory and reduces the power
consumption to the Standby level, IDD1.
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation. When Output Enable, G, is at VIH
the outputs are high impedance. Output Enable,
G, can be used to inhibit the data output during a
burst read operation.
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able (also see Latch Enable, L).
Reset/Power-Down (RP). The Reset/Power-
Down pin can be used to apply a Hardware Reset
to the memory.
A Hardware Reset is achieved by holding Reset/
Power-Down Low, VIL, for at least tPLPH. When
Reset/Power-Down is Low, VIL, the Status Regis-
ter information is cleared and the power consump-
tion is reduced to power-down level. The device is
deselected and outputs are high impedance. If Re-
set/Power-Down goes low, VIL,during a Block
Erase, a Write to Buffer and Program or a Block
Protect/Unprotect the operation is aborted and the
data may be corrupted. In this case the Ready/
Busy pin stays low, VIL, for a maximum timing of
tPLPH + tPHRH, until the completion of the Reset/
Power-Down pulse.
After Reset/Power-Down goes High, VIH, the
memory will be ready for Bus Read and Bus Write
operations after tPHQV. Note that Ready/Busy
does not fall during a reset, see Ready/Busy Out-
put section.
In an application, it is recommended to either as-
sociate the Reset/Power-Down pin, RP, with the
reset signal of the microprocessor, or to ensure
that the Reset/Power-Down pin is kept Low during
Power-on. Otherwise, if a reset operation occurs
while the memory is performing an Erase or Pro-
gram operation, the memory may output the Sta-
tus Register information instead of being initialized
to the default Asynchronous Random Read.
Latch Enable (L). The Bus Interface is config-
ured to latch the Address Inputs on the rising edge
of Latch Enable, L. In synchronous bus operations
the address is latched on the active edge of the
Clock when Latch Enable is Low, VIL or on the ris-
ing of Latch Enable, whichever occurs first. Once
latched, the addresses may change without affect-
ing the address used by the memory. When Latch
Enable is Low, VIL, the latch is transparent.
Clock (K). The Clock, K, is used to synchronize
the memory with the external bus during Synchro-
nous Bus Read operations. The Clock can be con-
figured to have an active rising or falling edge. Bus
signals are latched on the active edge of the Clock
during synchronous bus operations. In Synchro-
nous Burst Read mode the address is latched on
the first active clock edge when Latch Enable is
low, VIL, or on the rising edge of Latch Enable,
whichever occurs first.
During asynchronous bus operations the Clock is
not used.
Valid Data Ready (R). The Valid Data Ready
output, R, is an open drain output that can be used
to identify if the memory is ready to output data or
not. The Valid Data Ready output is only active
during Synchronous Burst Read operations when
the Burst Length is set to Continuous. The Valid
Data Ready output can be configured to be active
on the clock edge of the invalid data read cycle or
11/61
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