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PDF M58BF008B100D6T Data sheet ( Hoja de datos )
| Número de pieza | M58BF008B100D6T | |
| Descripción | 8 Mbit 256Kb x32 / Burst Flash Memory | |
| Fabricantes | ST Microelectronics | |
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M58BF008
8 Mbit (256Kb x32, Burst) Flash Memory
PRELIMINARY DATA
s SUPPLY VOLTAGE
– VDD = 5V Supply Voltage
– VDDQ = 3.3V Input/Output Supply Voltage
– Optional VPP = 12V for fast Program and Erase
s CONFIGURABLE OPTIONS
– Synchronous or Asynchronous write mode
– Burst Wrap/No-wrap default
– Critical Word X (3 or 4) and Burst Word
Y (1 or 2) latency times
s ACCESS TIME
– Synchronous X-Y-Y-Y Burst Read
up to 40MHz
– Asynchronous Read: 100ns
s PROGRAMMING TIME: 10µs typical
s MEMORY BLOCKS
– 32 equal Main blocks of 256 Kbit
– One Overlay block of 256 Kbit
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: F0h
– Version Code: 0-7h
DESCRIPTION
The M58BF008 is a family of 8 Mbit non-volatile
Flash memories that can be erased electrically at
the block level and programmed in-system. Family
members are configured during product testing for
a specific Synchronous or Asynchronous Write
mode, a Burst default of Wrap or No-wrap and for
Critical Word X = 3 or 4 and Burst Word Y = 1 or 2
latency times. The Main memory array matrix al-
lows each of the 32 equal blocks of 256 Kbit to be
erased separately and re-programmed without af-
fecting other blocks. The memory features a
256 Kbit Overlay block having the same address
space as the first Main memory block. The Overlay
block provides a secure storage area that is con-
trolled by special Instructions and an external in-
put. A separate supply VDDQ allows the Input/
Output signals to be at 3.3V levels, while the main
supply VDD is 5V.
BGA
LBGA80 (ZA)
10 x 8 solder balls
PQFP80 (D)
Figure 1. Logic Diagram
VDD VDDQ VPP
18
A17-A0
32
DQ31-DQ0
CLK
RP
E
G
GD
W
LBA
WR
BAA
M58BF008
VSS VSSQ
AI02656B
February 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/36
1 page  
M58BF008
ORGANISATION
The M58BF008 has a data path width of 32 bit
(Double-Word) and is organised as a Main memo-
ry array of 32 blocks of 256 Kbit plus an Overlay
block of 256 Kbit having the same address space
as the first Main memory block. The memory map
is shown in Table 3.
The memory is addressed by A0-A17 which are
static for Asynchronous or latched for Synchro-
nous operation. Data Input/Output is static or
latched on DQ0-DQ31, these signals output data,
Table 3. Block Addresses
#
Size
(Kbit)
31 256
30 256
29 256
28 256
27 256
26 256
25 256
24 256
23 256
22 256
21 256
20 256
19 256
18 256
17 256
16 256
15 256
14 256
13 256
12 256
11 256
10 256
9 256
8 256
7 256
6 256
5 256
4 256
3 256
2 256
1 256
0 256
Overlay Block
256
Address Range
3E000-3FFFF
3C000-3DFFF
3A000-3BFFF
38000-39FFF
36000-37FFF
34000-35FFF
32000-33FFF
30000-31FFF
2E000-2FFFF
2C000-2DFFF
2A000-2BFFF
28000-29FFF
26000-27FFF
24000-25FFF
22000-23FFF
20000-21FFF
1E000-1FFFF
1C000-1DFFF
1A000-1BFFF
18000-19FFF
16000-17FFF
14000-15FFF
12000-13FFF
10000-11FFF
0E000-0FFFF
0C000-0DFFF
0A000-0BFFF
08000-09FFF
06000-07FFF
04000-05FFF
02000-03FFF
00000-01FFF
00000-01FFF
status or signatures read from the memory, or they
input data to be programmed or Instruction com-
mands to the Command Interface.
Asynchronous mode
Memory control is provided by Chip Enable E, Out-
put Enable G and Write Enable W for read and
write operations.
Synchronous mode
Memory control is provided by Load Burst Address
LBA which loads a read or write address. A Syn-
chronous Single Read or a Synchronous Burst
Read is performed under control of Output Enable
G. Synchronous Write is controlled by Write/Read
Enable WR, Load Burst Address LBA and Write
Enable W. Internal advance of the burst address is
controlled by Burst Address Advance BAA.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A17). The address signal
A17 is the MSB and A0 the LSB.
In the Asynchronous mode the addresses must be
stable before Chip Enable E and Write Enable W
go to VIL. They must remain stable during the read
or write cycle.
In the Synchronous modes, the addresses are
latched by the rising edge of the System Clock
CLK when both Latch Burst Address LBA and
Chip Enable E are at VIL. The addresses are
latched for a read operation if Write/Read WR is at
VIH or for a write operation when it is at VIL.
Data Input/Output (DQ0-DQ31). The data signal
DQ31 is the MSB and DQ0 the LSB. Commands
are input on DQ0-DQ7.
Data input is a Double-Word to be programmed in
the memory or an Instruction command to the
Command Interface. Data is read from the Main or
Overlay memory blocks, the Status Register or the
Electronic Signature.
In the Asynchronous mode data is read when the
addresses are stable and Chip Enable E and Out-
put Enable G are at VIL. Commands or address/
data are written when Chip Enable E and Write W
are at VIL.
In the Synchronous mode, after addresses are
latched, data is read on a rising edge of the Sys-
tem Clock CLK when Chip Enable E is at VIL and
if Output Enable was at VIL on the previous rising
clock edge. Data is written on a rising edge of the
System Clock CLK when Chip Enable E and Write
Enable W are at VIL.
The outputs are high impedance when Chip En-
able E or Output Enable G are at VIH, or when Out-
put Disable GD is at VIL. Outputs are also high
impedance when System Reset RP is at VIL.
5/36
5 Page 
M58BF008
Table 8. Status Register Bits
Mne-
monic
Bit
Name
P/ECS 7 P/E.C. Status
PESS
6
Program/Erase
Suspend Status
ES 5 Erase Status
PS 4 Program Status
VPPS
3 VPP Status
Reserved 2
OBEB
1
Overlay Block
Enable Bit
OBS
0
Overlay Block
Status
Logic
Level
Definiti on
Note
’1’ Ready
’0’ Busy
Indicates the P/E.C. status, check during
Program or Erase
‘1’ Suspend
‘0’
In Progress or
Completed
On Program/Erase Suspend instruction both
P/ECS and PESS bits are set to ‘1’.
Either ES bit or PS bit is set to ‘1’.
PESS and either ES or PS bits remain at ‘1’
until Erase Resume instruction is given.
’1’ Erase Error or
ES bit is set to ‘1’ if either PESS instruction is
Erase Suspend given or Erase operation fails. If ES bit is ‘1’,
’0’ Erase Success check PESS bit.
’1’ Program Error or PS bit is set to ‘1’ if either PESS instruction is
Program Suspend given or Program operation fails. If PS bit is ‘1’,
’0’ Program Success check PESS bit.
’1’ VPP Invalid
’0’ VPP OK
VPPS bit is set to ‘1’ if initially VPP is not VPPH
nor VPP1, when Program or Erase Instruction
are executed.
’1’ Enabled
’0’ Disabled
’1’ Activated
’0’ Not Activated
OBEB bit is set to ‘1’ when Overlay Block is
Enabled.
OBS bit is set to ‘1’ when OBEB is ‘1’ and VPP
is in the range VPP1 or VPPH.
Erase (EE). The Erase instruction consists of two
write cycles, the first is the erase set-up command
20h at the address 00000h. This is followed by the
Erase Confirm command D0h written to an ad-
dress within the block to be erased. If the second
is not the Erase Confirm command the Status
Register bits 4 and 5 are set to ’1’ and the instruc-
tion aborts. While erasing is in progress only the
Read Status Register and Erase Suspend instruc-
tions are valid.
Blocks are erased one at a time. An erase opera-
tion sets all bits in a block to ’1’. The erase algo-
rithm automatically programs all bits to ’0’ before
erasing the block to all ’1’s.
Read operations output the Status Register after
the erase operation has started. The Status Reg-
ister bit 7 is ’0’ while the erase is in progress and is
set to ’1’ when it is completed. After completion the
Status Register bit 5 is set to ’1’ if there has been
an erase failure.
Erasure should not be attempted when the VPP
Program/Erase Supply Voltage is out of the range
VPP1 or VPPH as the results will be uncertain. The
Status Register bit 3 is set to ’1’ if VPP is not within
the allowed ranges when erasing is attempted or if
it falls out of the ranges during erase execution.
The erase operation aborts if VPP drops out of the
allowed range or if Reset/Power-down RP falls to
VIL. As data integrity cannot be guaranteed when
the erase operation is aborted, the erase must be
repeated.
A Clear Status Register instruction must be given
to clear the Status Register bits.
Overlay Block Erase (OBEE). The
Overlay
Block Erase instruction consists of two write cy-
cles, the first is the Overlay block erase set-up
command 02h at the address 00000h. This is fol-
lowed by the Overlay Block Erase Confirm com-
mand 0Dh written to an address within the Overlay
block. If the second is not the Overlay Block Erase
Confirm command the Status Register bit 5 is set
to ’1’ and the instruction aborts. While erasing is in
progress only the Read Status Register instruction
is valid.
The operation is executed as described for the
Erase (EE) instruction of the Main memory array.
A Clear Status Register instruction must be given
to clear the Status Register bits.
11/36
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