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PDF M54HC73 Data sheet ( Hoja de datos )
| Número de pieza | M54HC73 | |
| Descripción | DUAL J-K FLIP FLOP WITH PRESET AND CLEAR | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M54HC73
M74HC73
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
. HIGH SPEED
fMAX = 75 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 2 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS73
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC73F1R
M 74H C7 3M 1R
M 74HC 73 B1 R
M 74H C7 3C 1R
DESCRIPTION
The M54/74HC73 is a high speed CMOS DUAL J-K
FLIP FLOP WITH CLEAR fabricated in silicon gate
C2MOS technology. It has the same high speed per-
formance of LSTTL combined with true CMOS low
power consumption. Depending on the logic level
applied to J and K inputs, this device changes state
on the negative going transition of clock input pulse
(CK). The clear function is accomplished inde-
pendently of the clock condition when the clear input
(CLR) is taken low. All inputs are equipped with pro-
tection circuits against static discharge and transient
excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS (top view)
October 1992
NC =
No Internal
Connection
1/11
1 page  
M54/M74HC73
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 2.0
tTHL Time
4.5
30 75
8 15
95 110
19 22 ns
6.0 7 13 16 19
tPLH Propagation
tPHL Delay Time
(CLOCK - Q)
2.0
4.5
6.0
42 125 155 190
14 25 31 38 ns
12 21 26 32
tPLH Propagation
tPHL Delay Time
(CLEAR - Q)
2.0
4.5
6.0
54 145 180 220
18 29 36 44 ns
15 25 31 37
fMAX Maximum Clock 2.0
Frequency
4.5
6 15
4.8
4
30 60 24 20 MHz
6.0 35 80 28 24
tW(H)
tW(L)
Minimum Pulse
Width
(CLOCK)
2.0
4.5
6.0
18 75
6 15
6 13
95 110
19 22 ns
16 19
tW(L) Minimum Pulse
Width
(CLEAR)
2.0
4.5
6.0
21 75
7 15
6 13
95 110
19 22 ns
16 19
ts Minimum Set-up 2.0
Time
4.5
30 75
8 15
95 110
19 22 ns
6.0 6 13 16 19
th Minimum Hold 2.0
Time
4.5
000
0 0 0 ns
6.0 0 0 0
tREM Minimum
Removal Time
2.0
4.5
25 75
7 15
95 110
19 22 ns
6.0 6 13 16 19
CIN Input Capacitance
5 10 10 10 pF
CPD (*) Power Dissipation
Capacitance
35
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC/2 (per FLIP/FLOP)
5/11
5 Page 
M54/M74HC73
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
11/11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet M54HC73.PDF ] | |
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