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PDF PEF3460E Data sheet ( Hoja de datos )
| Número de pieza | PEF3460E | |
| Descripción | Single channel T3/E3 Framer & Line Interface for ATM/ Frame Relay and PPP/IP | |
| Fabricantes | Infineon Technologies AG | |
| Logotipo |  |
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Product Overview, DS2, Dec. 2002
TE3-FALC
omT3/E3 Framer & Line Interface for
.cATM, Frame Relay & PPP/IP
UPEF 3460 E, Version 1.2
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1 page  
TE3-FALC
PEF 3460 E
Overview
1 Overview
This Product Overview provides an overview about the functionality of the "T3/E3
Framer & Line Interface for ATM, Frame Relay & PPP/IP" TE3-FALC (PEF 3460 E).
Note: Some features mentioned in this document are options for future firmware
enhancements and not supported with the current release of firmware. These
options are marked with a preceding " " symbol.
The TE3-FALC is a complete solution for a T3/E3 broadband interface. It includes DS3/
E3 framing, analog line interface, two jitter attenuators and the mapping of ATM or
HDLC-framed PPP. The TE3-FALC also integrates a microcontroller which handles the
device configuration, processes alarms and gathers statistics in accordance with the
relevant managed MIB objects. A firmware image needs to be uploaded as part of the
initialization of the device.
On line side the TE3-FALC interfaces to a 75 ohm co-axial cable via transformers. Highly
accurate analog pulse shaping removes the need to measure cable length and set the
Line Build Out.
On the system side, industry standard UTOPIA and POS-PHY interface as well as
UTOPIA-L2X and serial clock/data port are provided. This allows the TE3-FALC to be
connected to a wide array of Layer 2/3 & 4 network processors.
Product Overview
5
DS2, 2002-12-10
5 Page 
1.3 Minimum System
TE3-FALC
PEF 3460 E
Overview
clkin
frequency
1:1
Cp
1:1
R1 C1
R2
T3/E3
75 Ω
+/- 1%
100 nf 37.5 Ω
+/- 1%
tmc, tck, tdi p[2:0] rclkout tclki, rsync clkin
tdo, trst_n
(optional)
RL1 clkout
R1
C1
RL2
R2 TE3-FALC
XL1 PEF 3460 E
stclk
std[7:0], stprty
stenb_n, stsx, stpa
srclk
srd[7:0], srprty
srenb_n, srsx, srpa
R2
XL2
dtxdin
dtgckout
Cp
37 pf
mpd[7:0],
mpa[11:0], msel,
mpwr_n, mprd_n
mpcs_n, mpint_n
drxdout
drgckout
mpim[4:0] cfg[2:0] por_n
µProcessor Boot
mode
mode
TE3FALC apps#3
Figure 2 TE3-FALC Minimum System (UTOPIA or Serial Interface)
The above diagram shows the minimum system connectivity for the TE3-FALC showing
all required signals to operate the device either with an UTOPIA interface or a serial
interface. The TE3-FALC can operate from a single reference clock, CLKIN, and support
software switching between T3 and E3 without any hardware change. When using a
POS-PHY or UTOPIA-L2X interface the TE3-FALC is also able to switch between
mapping ATM cells to PPP packets without any hardware change. Unused pins should
be either left unconnected or tied to their inactive state as recommended in the pin
description tables.
There are three hardware configuration selection pin groups. The first is P[2:0] which
select the frequency range of CLKIN. The second is MPIM[4:0] which selects the type of
microprocessor mode being used and the third, CFG[2:0], selecting the start up boot
mode.
Product Overview
11
DS2, 2002-12-10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PEF3460E.PDF ] | |
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