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PDF PEF2015 Data sheet ( Hoja de datos )
| Número de pieza | PEF2015 | |
| Descripción | ICs for Communications | |
| Fabricantes | Infineon Technologies AG | |
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Hay una vista previa y un enlace de descarga de PEF2015 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ICs for Communications
Extended PCM Interface Controller
EPIC®-1
PEB 2055 / PEF 2055 Versions A3
EPIC®-S
PEB 2054 / PEF 2054 Versions 1.0
User’s Manual 02.97
1 page  
PEB 2055
PEF 2055
Table of Contents
Page
4.2.6.8 Version Number Status Register (VNSR) . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.1.1 IOM® and SLD Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.2 Configuration of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
5.2.1 PCM Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
5.2.1.1 PCM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
5.2.1.2 PCM Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
5.2.1.3 PCM Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
5.2.2 Configurable Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
5.2.2.1 CFI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
5.2.2.2 CFI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
5.2.2.3 CFI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
5.3 Data and Control Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.3.1 Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.3.2 Indirect Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
5.3.3 Memory Access Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
5.3.3.1 Access to the Data Memory Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
5.3.3.2 Access to the Data Memory Code (Tristate) Field . . . . . . . . . . . . . . . . . . . .139
5.3.3.3 Access to the Control Memory Data Field . . . . . . . . . . . . . . . . . . . . . . . . . .142
5.3.3.4 Access to the Control Memory Code Field . . . . . . . . . . . . . . . . . . . . . . . . . .144
5.4 Switched Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
5.4.1 CFI - PCM Time Slot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
5.4.2 Subchannel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
5.4.3 Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
5.4.3.1 CFI - CFI Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
5.4.3.2 PCM - PCM Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
5.4.4 Switching Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
5.4.4.1 Internal Procedures at the Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . .167
5.4.4.2 How to Determine the Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
5.4.4.3 Example: Switching of Wide Band ISDN Channels with the EPIC® . . . . . . .172
5.5 Preprocessed Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
5.5.1 Initialization of Preprocessed Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
5.5.2 Control/Signaling (CS) Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
5.5.2.1 Registers used in Conjunction with the CS Handler . . . . . . . . . . . . . . . . . .188
5.5.2.2 Access to Downstream C/I and SIG Channels . . . . . . . . . . . . . . . . . . . . . .190
5.5.2.3 Access to the Upstream C/I and SIG Channels . . . . . . . . . . . . . . . . . . . . . .191
5.5.3 Monitor/Feature Control (MF) Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
5.5.3.1 Registers used in Conjunction with the MF Handler . . . . . . . . . . . . . . . . . .195
5.5.3.2 Description of the MF Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . .200
5.6 µP Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Semiconductor Group
5
02.97
5 Page 
PEB 2055
PEF 2055
Overview
1.3 Pin Definitions and Functions
Pin No. Symbol Input (I) Function
EPIC-S EPIC
Output (O)
30 30 CS
I
Chip Select; active low. A “low” on this line
selects the EPIC for read/write operations.
29 29 WR, I
R/W
Write, active low, Siemens/Intel bus mode.
When “low”, a write operation is indicated.
Read/Write, Motorola bus mode.
When “high” a valid µP-access identifies a read
operation, when “low” it identifies a write access.
28 28 RD, DS I
Read, active low, Siemens/Intel bus mode.
When “low” a read operation is indicated.
Data Strobe, Motorola bus mode.
A rising edge marks the end of a read or write
operation.
19 19 AD0, D0 I/O
20 20 AD1, D1 I/O
21 21 AD2, D2 I/O
22 22 AD3, D3 I/O
23 23 AD4, D4 I/O
24 24 AD5, D5 I/O
25 25 AD6, D6 I/O
26 26 AD7, D7 I/O
Address/Data Bus; multiplexed bus mode.
Transfers addresses from the µP-system to the
EPIC and data between the µP and the EPIC.
Data Bus; demultiplexed bus mode.
Transfers data between the µP and the EPIC.
When driving data the pins have push pull
characteristic, otherwise they are in high
impedance state.
31 31 ALE I
Address Latch Enable
ALE controls the on chip address latch in
multiplexed bus mode. While ALE is “high”, the
latch is transparent. The falling edge latches the
current address. During the first read/write
access following reset ALE is evaluated to select
the bus mode.
32 32 INT
O
(OD)
Interrupt Request, active low.
This signal is activated when the EPIC requests
an interrupt. Due to the open drain (OD)
characteristic of INT multiple interrupt sources
can be connected together.
44 44 RES I
Reset
A “high” forces the EPIC into reset state.
16 16 PFS I
PCM Interface Frames Synchronization
Semiconductor Group
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PEF2015.PDF ] | |
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