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PDF PEB20321 Data sheet ( Hoja de datos )
| Número de pieza | PEB20321 | |
| Descripción | Multichannel Network Interface Controller for HDLC MUNICH32X | |
| Fabricantes | Siemens Semiconductor Group | |
| Logotipo |  |
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ICs for Communications
Multichannel Network Interface Controller for HDLC
MUNICH32X
PEB 20321 Version 2.2
Data Sheet 1998-08-01
DS 1
1 page  
PEB 20321
Table of Contents
Page
11.2.5
11.2.6
11.2.7
SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
IOM®-2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
12
12.1
12.1.1
12.1.2
12.2
12.2.1
12.2.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
12.11
12.11.1
12.11.2
12.11.3
Host Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
Control and Configuration Block (CCB) in Host Memory . . . . . . . . . . . . .243
Serial PCM Core CCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
LBI CCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
Action Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
Serial PCM Core Action Specification . . . . . . . . . . . . . . . . . . . . . . . . . . .246
LBI Action Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
Serial PCM Core Interrupt Vector Structure . . . . . . . . . . . . . . . . . . . . . .249
Interrupt Bit Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
Time Slot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Channel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
Current Receive and Transmit Descriptor Addresses . . . . . . . . . . . . . . .271
Receive Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
Transmit Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
Serial PCM Core DMA Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
Interrupt Queues Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
Serial PCM Core Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
LBI DMA Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
Peripheral Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
13 Boundary Scan Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
14
14.1
14.2
14.3
14.4
14.5
14.6
14.6.1
14.6.1.1
14.6.1.2
14.6.1.3
14.6.2
14.6.3
14.6.3.1
14.6.3.2
14.6.4
14.6.5
14.6.6
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Important Electrical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
PCI Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
PCI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
De-multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
Local Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
Local Bus Interface Timing in Slave Mode . . . . . . . . . . . . . . . . . . . . . . .307
Local Bus Interface Timing in Master Mode . . . . . . . . . . . . . . . . . . . . . .310
PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
SSC Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
Semiconductor Group
5
1998-08-01
5 Page 
PEB 20321
Introduction
1.2 New or Changed from MUNICH32, PEB 20320
• Symmetrical Rx and Tx Buffer Descriptor formats for faster switching
• Improved Tx idle channel polling process, which significantly reduces bus occupancy
of idle Tx channels
• Additional PCM modes supported: 3.088 Mbit/s, 6.176 Mbit/s, 8.192 Mbit/s
• 32-bit PCI bus Master/Slave interface (33 MHz) with integrated DMA controllers for
higher performance, and lower development effort and risk
• Enhanced Interrupt Structure providing:
separate serial PCM Rx and Tx Interrupt Queues in host memory,
separate DMA related LBI Rx and Tx Interrupt Queues in host memory,
dedicated LBI pass-through, SSC, General Purpose bus and IOM®-2 Peripheral
Interrupt Queue in host memory
• Slave read capability of serial PCM core, LBI, SSC and IOM®-2 read/write registers
• Time Slot Shift capability
programmable from -4 clock edges to +3 clock edges relative to synchronization
pulse,
programmable to sample Tx data at either clock falling or rising edge,
programmable to sample Rx data at either clock falling or rising edge,
• Software initiated Action Request via a bit field in the Command register
• Tx End-of-Packet transmitted-on-wire interrupt capability per channel
• Tx packet size increased to 16 Kbytes
• Rx packet size 8 kbyte limit interrupt disable
• Rx Enable bit field of the MODE1 register
• Rx Interrupt Disable bit field of the MODE1 register
• Tx data tristate control line (TXDEN)
• Synchronized data transfer in TMA mode for complete transparency when using
fractional T1/PRI channels
• Integrated Local Bus Interface (LBI), which allows connection to peripherals that do
not provide a PCI bus interface
• IOM®-2 interface with single and double data rate clock
• Collision control on S/T interface by QUAT-S (PEB 2084) via data ready control line
(DRDY)
• Synchronous Serial Control (SSC) interface
• 16-bit General Purpose Bus (available, when LBI and SSC are not used)
• Internal Descriptor and Table Dump capability for software development purposes
• Little/Big Endian data formats selectable via a bit field in Configuration register
Semiconductor Group
11
1998-08-01
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PEB20321.PDF ] | |
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