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PDF lCL8068ACJD Data sheet ( Hoja de datos )
| Número de pieza | lCL8068ACJD | |
| Descripción | 14-Bit/16-Bit / Microprocessor- Compatible / 2-Chip / A/D Converter | |
| Fabricantes | Intersil | |
| Logotipo |  |
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August 1997
ICL8052/ICL7104,
ICL8068/ICL7104
14-Bit/16-Bit, Microprocessor-
Compatible, 2-Chip, A/D Converter
Features
• 16-Bit/14-Bit Binary Three-State Latched Outputs Plus
Polarity and Overrange
• Ideally Suited for Interface to UARTs and
Microprocessors
• Conversion on Demand or Continuously
• Guaranteed Zero Reading for 0V Input
• True Polarity at Zero Count for Precise Null Detection
• Single Reference Voltage for True Ratiometric
Operation
• Onboard Clock and Reference
• Auto-Zero, Auto-Polarity
• Accuracy Guaranteed to 1 Count
• All Outputs TTL Compatible
• ±4V Analog Input Range
• Status Signal Available for External Sync, A/Z in
Preamp, Etc.
Description
The ICL7104, combined with the ICL8052 or ICL8068,
forms a member of Intersil’ high performance A/D converter
family. The ICL7104-16, performs the analog switching and
digital function for a 16-bit binary A/D converter, with full
three-state output, UART handshake capability, and other
outputs for easy interfacing. The ICL7014-14 is a 14-bit
version. The analog section, as with all Intersil’ integrating
converters, provides fully precise Auto-Zero, Auto-Polarity
(including ±0 null indication), single reference operation,
very high input impedance, true input integration over a
constant period for maximum EMI rejection, fully
rationmetric operation, over-range indication, and a
medium quality built-in reference. The chip pair also offers
optional input buffer gain for high sensitivity applications, a
built-in clock oscillator, and output signals for providing an
external Auto-Zero capability in preconditioning circuitry,
synchronizing external multiplexers, etc.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.
NO.
ICL8052CPD
0 to 70 14 Ld PDIP
E14.3
lCL8052CDD
0 to 70 14 Ld CERDIP F14.3
lCL8052ACPD
0 to 70 14 Ld PDIP
E14.3
ICL8052ACDD
0 to 70 14 Ld CERDIP F14.3
ICL8068CDD
0 to 70 14 Ld CERDIP F14.3
ICL8068ACDD
0 to 70 14 Ld CERDIP F14.3
lCL8068ACJD
0 to 70 14 Ld CERDIP F14.3
ICL7104-14CPL
0 to 70 40 Ld PDIP
E40.6
lCL7104-16CPL
0 to 70 40 Ld PDIP
E40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
5-6
File Number 3091.1
1 page  
ICL8052/ICL7104, ICL8068/ICL7104
Absolute Maximum Ratings
ICL8052, ICL8068
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
Differential Input Voltage
(8068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30V
(8052) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6V
Input Voltage (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
Output Short Circuit Duration All Outputs (Note 3). . . . . . . Indefinite
ICL7104
V+ Supply (GND to V+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
V++ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32V
Positive Supply Voltage (GND to V++) . . . . . . . . . . . . . . . . . . . . 17V
Negative Supply Voltage (GND to V-). . . . . . . . . . . . . . . . . . . . .-17V
Analog Input Voltage (Pins 32 - 39)(Note 4). . . . . . . . . . . . V++ to V-
Digital Input Voltage
(Pins 2 - 30) (Note 5) . . . . . . . . . . . . (GND - 0.3V) to (V+ + 0.3V)
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
14 Ld PDIP Package . . . . . . . . . . . . . . 100
N/A
40 Ld PDIP Package . . . . . . . . . . . . . .
60
N/A
14 Ld CERDIP Package . . . . . . . . . . .
75
20
Maximum Junction Temperature (Ceramic Package) . . . . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
3. Short circuit may be to ground or either supply. Rating applies to 70oC ambient temperature.
4. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
5. Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latchup. For this
reason it is recommended that the power supply to the ICL7104 be established before any inputs from sources not on that supply are
applied.
ICL7104 Electrical Specifications V+ = +5V, V++ = +15V, V- = -15V, TA = 25oC, fCLOCK = 200kHz
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN TYP
Clock Input, CLK 1
Comparator I/P, COMP IN (Note 6)
Inputs with Pulldown, MODE
Inputs with Pullups
SEN, R/H
LBEN, MBEN, HBEN, CE/LD (Note 7)
IIN VIN = +5V to 0V
IIN VIN = 0V to +5V
IIH VIN = +5V
IIL VIN = 0V
IIH VIN = +5V
IIL VIN = 0V
±2 ±7
-10 ±0.001
15
-10 ±0.01
-10 ±0.01
-30 -5
Input High Voltage, All Digital Inputs
Input Low Voltage, All Digital Inputs
Digital Outputs Three-Stated On,
LBEN, MBEN (16 Only), HBEN, CE/LD
BIT n, POL, OR (Note 8)
Digital Outputs Three-Stated Off
Bit n, POL, OR
VIH
VIL
VOL
VOH
VOH
IOL
IOL = 1.6mA
IOH = -10µA
IOH = -240µA
0 ≤ VOUT ≤ V+
2.5 2.0
- 1.5
- 0.27
- 4.5
2.4 3.5
-10 ±0.001
Non Three-State Digital Output
STTS
Clock 2
Clock 3 (-14 Only)
VOL
VOH
VOL
VOH
VOL
VOH
IOL = 3.2mA
IOH = -400µA
IOL= 320µA
IOH = -320µA
IOL = 1.6mA
IOH = -320µA
- 0.3
2.4 3.3
- 0.5
- 4.5
- 0.27
2.4 3.5
MAX
±30
10
30
10
10
-1
-
1.0
0.4
-
-
+10
0.4
-
-
-
0.4
-
UNITS
µA
µA
µA
µA
µA
µA
V
V
V
V
V
µA
V
V
V
V
V
V
5-10
5 Page 
ICL8052/ICL7104, ICL8068/ICL7104
CLOCK 1 H
(PIN 25) L
tCWH
EITHER: H
MODE PIN L
OR
tMW
INTERNAL
LATCH PULSE IF
MODE “HI”
INTERNAL UART
MODE NORM
H
CE/LD L
tCEL
tME
SEN
(EXTERNAL
SIGNAL)
HBEN
H
DON’T CARE
L
tMB
H
L
O/R, POL H
01-14 L
H
LBEN L
tSM
IGNORED
tCEH
EXT
EXT
tCBL
DATA VALID, STABLE
tCDH
DON’T CARE
IGNORED
tSS
tCBH
tCDL
STABLE
tCEZ
tCBZ
DON’T CARE
BITS 1-5
HANDSHAKE MODE
TRIGGERED BY
DATA VALID, STABLE
OR THREE-STATE
-16 HAS EXTRA (MBEN) PHASE
FIGURE 5. HANDSHAKE MODE TIMING DIAGRAM
THREE-STATE WITH PULLUP
Detailed Description
ANALOG SECTION
Figure 6 shows the equivalent Circuit of the Analog Section
of both the ICL7104/8052 and the ICL7104/8068 in the 3
different phases of operation. If the Run/Hold pin is left open
or tied to V+, the system will perform conversions at a rate
determined by the clock frequency: 131,072 for - 16 and
32,368 for - 14 clock periods per cycle (see Figure 8
conversion timing).
Auto-Zero Phase I (Figure 6A)
During Auto-Zero, the input of the buffer is shorted to analog
ground thru switch 2, and switch 1 closes a loop around the
integrator and comparator. The purpose of the loop is to
charge the Auto-Zero capacitor until the integrator output no
longer changes with time. Also, switches 4 and 9 recharge
the reference capacitor to VREF.
Input Integrate Phase II (Figure 6B)
During input integrate the Auto-Zero loop is opened and the
analog input is connected to the buffer input thru switch 3.
(The reference capacitor is still being charged to VREF
during this time.) If the input signal is zero, the buffer,
integrator and comparator will see the same voltage that
existed in the previous sate (Auto-Zero). Thus the integrator
output will not change but will remain stationary during the
entire Input Integrate cycle. If VIN is not equal to zero, an
unbalanced condition exists compared to the Auto-Zero
phase, and the integrator will generate a ramp whose slope
is proportional to VIN. At the end of this phase, the sign of
the ramp is latched into the polarity F/F.
Deintegrate Phase III (Figures 6C and 6D)
During the Deintegrate phase, the switch drive logic uses the
output of the polarity F/F in determining whether to close
switches 6 and 9 or 7 and 8. If the input signal was positive,
switches 7 and 8 are closed and a voltage which is VREF
more negative than during Auto-Zero is impressed on the
buffer input. Negative inputs will cause +VREF to be applied
to the buffer input via switches 6 and 9. Thus, the reference
capacitor generates the equivalent of a (+) reference or a (-)
reference from the single reference voltage with negligible
error. The reference voltage returns the output of the integra-
tor to the zero-crossing point established in Phase I. The
time, or number of counts, required to do this is proportional
to the input voltage. Since the Deintegrate phase can be
twice as long as the Input integrate phase, the input voltage
required to give a full scale reading = 2VREF.
NOTE: Once a zero crossing is detected, the system automatically
reverts to Auto-Zero phase for the leftover Deintegrate time (unless
RUN/HOLD is manipulated, see RUN/HOLD input in detailed
description, digital section).
5-16
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet lCL8068ACJD.PDF ] | |
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