|
|
PDF LC8901 Data sheet ( Hoja de datos )
| Número de pieza | LC8901 | |
| Descripción | Digital Audio Interface Receiver | |
| Fabricantes | Sanyo | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LC8901 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
Ordering number : EN4079B
CMOS LSI
LC8901, 8901Q
Digital Audio Interface Receiver
Overview
The LC8901 and LC8901Q are LSIs for use in IEC958,
EIAJ CP-1201 format data transmission between digital
audio equipment. These LSIs are used on the receiving
side, and handle synchronization with the input signal and
demodulation of that signal to a normal format signal.
Package Dimensions
unit: mm
3025B-DIP42S
[LC8901]
Features
• On-chip PLL circuit synchronizes with the transmitted
IEC958, EIAJ CP-1201 format signal.
• Provides 20-bit LSB first and 16-bit MSB first audio
data output functions.
• Microprocessor interface for mode settings and code
output
• System clock can be selected to be either 384fs or 512fs.
• Provides both a digital source mode and an analog
source mode.
• Fabricated in a Si-gate CMOS process.
• 5 V single-voltage power supply
unit: mm
3148-QIP44M
[LC8901Q]
SANYO: DIP42S
SANYO: QIP44M
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D3095HA (OT)/52593JN/7202JN No. 4079-1/15
1 page  
LC8901, 8901Q
LC8901Q (QIP44M)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Symbol
DIN5
DIN6
DOUT1
DOUT2
RC1
RC2
LPF
STOP
TEST1
TEST2
DVDD
AVDD
R
AGND
VIN
VCO
DGND
CLK
XSYS
XIN1
XIN2
DVDD
LOCK
ERROR
FS256
CLKOUT
EMPHA
DGND
BCLK
DATAOUT
LRCK
SUB1
SUB2
DO
DI
CE
CL
XMODE
DVDD
DIN1
DIN2
DIN3
DIN4
DGND
I/O Pin function and circuit operation
I
Data input pins without built-in amplifiers
I
O
Input data through output
O
I
RC oscillator connection
O
I High: LPF time constant switching mode, low: fixed mode. This pin is normally high.
I High: VCO operation stopped, Low: normal operation
I
Test pins (These pins are normally low.)
I
— Digital system power supply
— Analog system power supply
I VCO oscillator band adjustment
— Analog system ground
I VCO free-running oscillator setup
O PLL low-pass filter
— Digital system ground
I Clock mode switching. High: 512fs, low: 384fs
I Crystal mode setting. High: crystal mode
I
Crystal oscillator connection
O
— Digital system ground
O High: PLL locked, low: unlocked
O Error mute signal output
O 256fs clock output
O VCO oscillator and crystal oscillator clock output
O High: emphasis present, low: no emphasis
— Digital system ground
O Bit clock output
O Audio data output
O Left/right clock output. High: left channel, low: right channel
O
Sampling frequency output
O
O Microprocessor interface output
I Microprocessor interface input
I Microprocessor interface chip enable input
I Microprocessor interface clock input
I Used to start system operation after power on.
— Digital system power supply
I
I
Data input pins with built-in amplifiers
I
I
— Digital system ground
No. 4079-5/15
5 Page 
LC8901, 8901Q
Microprocessor Interface Output
The table lists the content of the bits D0 to D15 in the microprocessor interface format.
Bit
D0
D1
D2
D3
D4
D5 to D12
D13 D15
Meaning
Invalid bit. A low level is always output.
Indicate the sampling frequency.
Correspond to the 2 external output port pins.
Indicates the copy flag.
Low: copy protected, high: copying allowed.
Outputs the first bit in the channel status bits.
These bits serially output the 8 bits of the channel status category code.
Invalid bit. A low level is always output.
Interpretation of Bits D1 and D2
Sampling frequency
D1
D2
32 kHz
H
H
44.1 kHz
L
L
48 kHz
L
H
#1
H
L
1. The #1 state is the state in which the data was cleared by a PLL lock error.
2. The initial settings of the modes immediately after the XMODE pin is switched from low to high are all low level.
However, D1 and D2 will indicate the #1 state.
3. The microprocessor data output registers are all cleared to 0 when PLL locking is lost. However, D1 and D2 will
indicate the #1 state.
4. The interval between two microprocessor data readout operations must be at least 6 ms. Also, when PLL locking is
lost the microprocessor must wait at least 6 ms after the error signal goes low before accessing data.
FS Code
The SUB1 and SUB2 pins indicate the input data sampling frequency.
Sampling frequency
SUB1
SUB2
32 kHz
H
H
44.1 kHz
L
L
48 kHz
L
H
#1
H
L
The #1 state is the state in which the data was cleared by a PLL lock error.
Lock and Errors
1. LOCK pin: This pin goes high when preamble detection has succeeded for 2 consecutive frames and thus indicates
the PLL locked state. This pin is low at all other times. In particular, it is low when the XMODE pin is low, when the
STOP pin is high, and in analog source mode.
2. ERROR pin: Goes high when an error exists in the input data or when the PLL circuit is in the unlocked state. When
the data returns to normal it holds the high level for about 200 to 300 ms and then falls to low. This period is
inversely proportional to the input data sampling frequency. This pin is high when the XMODE pin is low, when the
STOP pin is high, and in analog source mode.
3. Data processing when errors occur: The table below lists the data processing that is performed when an error occurs.
Error type
Continuous parity errors for up to 8 cycles
Continuous parity errors for 9 or more cycles
PLL lock error
Audio output data
The previous data value is output
All zero data is output
All zero data is output
C bit output data
Held
Held
Data is cleared and the #1 state is indicated.
Note: The term “C bit data” means data that was decoded from the channel status bit.
• When there is no data input to the data demodulation system, the system automatically switches from PLL
operation to the crystal oscillator and enters analog source mode.
• These pins indicate a state identical to a PLL lock error in any of the following cases: The STOP pin is high, the
XMODE pin is low, or the system is in analog source mode.
No. 4079-11/15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet LC8901.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LC8900KQ | Digital Audio Interface Receiver | Sanyo |
| LC8901 | Digital Audio Interface Receiver | Sanyo |
| LC8901Q | Digital Audio Interface Receiver | Sanyo |
| LC8902 | Digital Audio Interface Receiver | Sanyo |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |