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PDF LC876662B Data sheet ( Hoja de datos )

Número de pieza LC876662B
Descripción 8-Bit Single-Chip Microcontroller
Fabricantes Sanyo　
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No Preview Available ! LC876662B Hoja de datos, Descripción, Manual

Ordering number : ENN*6843
CMOS IC
LC876694B/78B/62B
8-Bit Single-Chip Microcontroller
Preliminary
Overview
The LC876694B/LC876678B/LC876662B are 8 bit single chip microcontrollers with the following on-chip functional
blocks :
- CPU: operable at a minimum bus cycle time of 100ns
- On-chip ROM Maximum Capacity : LC876694B
96K bytes
LC876678B
80K bytes
LC876662B
64K bytes
- On-chip RAM: 2048 bytes
- VFD automatic display controller / driver
- 16 bit timer / counter (can be divided into two 8 bit timers)
- 16 bit timer / PWM (can be divided into two 8 bit timers)
- timer for use as date / time clock
- High speed clock counter
- System clock divider function
- synchronous serial I/O port (with automatic block transmit / receive function)
- asynchronous / synchronous serial I/O port
- 12-channel × 8-bit AD converter
- Weak signal detector
- 15-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
(1) Read-Only Memory (ROM): LC876694B
LC876678B
LC876662B
98304 × 8 bits
81920 × 8 bits
65536 × 8 bits
(2) Random Access Memory (RAM): LC876694B/78B/62B 2048 × 9 bits
(3) Minimum Bus Cycle Time: 100ns (10MHz)
Note: The bus cycle time indicates ROM read time.
(4) Minimum Instruction Cycle Time: 300ns (10MHz)
Ver.1.01
51000
11901 RM (IM) SK No.6843-1/23

1 page




LC876662B pdf
Pin Assignment
LC876694B/78B/62B
S48/PG0
S49/PG1
S50/PG2
S51/PG3
P00
P01
P02
P03
VSS2
VDD2
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50 S19/PC3
49 S18/PC2
48 S17/PC1
47 S16/PC0
46 VDD3
45 S15/T15
44 S14/T14
43 S13/T13
42 S12/T12
41 S11/T11
40 S10/T10
39 S9/T9
38 S8/T8
37 S7/T7
36 S6/T6
35 S5/T5
34 S4/T4
33 S3/T3
32 S2/T2
31 S1/T1
SANYO: QIP100E
No.6843-5/23

5 Page





LC876662B arduino
LC876694B/78B/62B
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol
Operating
VDD(1)
supply voltage
range
Hold voltage VHD
Pull-down
voltage
Input high
voltage
VP
VIH(1)
VIH(2)
VIH(3)
VIH(4)
VIH(5)
VIH(6)
VIH(7)
Pins
VDD1=VDD2=VDD3
=VDD4
Conditions
0.294µs ≤ Tcyc
≤ 200µs
Ratings
VDD[V] min. typ. max.
4.5 6.0
VDD1
VP
RAM and the
register data are
kept in HOLD
mode.
4.5 to 6.0
2.0
-35
6.0
VDD
•Port 0,3: CMOS output
option
•Port 8
Port 0,3: N-ch open drain
output
Output disable
Output disable
•Port 1
•Port71,72,73
•P70 port input/interrupt
S16 to S51
Output disable
Output P-channel
Tr. OFF
P70 Weak signal input
Port 70
Watchdog timer
Output disable
Output disable
XT1, XT2, CF1, RES
4.5 to 6.0 0.3VDD
+0.7
4.5 to 6.0 0.3VDD
+0.7
4.5 to 6.0 0.3VDD
+0.7
4.5 to 6.0 0.3VDD
+1.0
4.5 to 6.0 0.75VDD
4.5 to 6.0 0.9VDD
4.5 to 6.0 0.75VDD
VDD
13.5
VDD
VDD
VDD
VDD
VDD
unit
V
Input low
voltage
VIL(1)
VIL(2)
VIL(3)
VIL(4)
VIL(5)
VIL(6)
VIL(7)
Operation
tCYC
cycle time
External system fEXCF(1)
clock
frequency
•Port 0,3: CMOS output
option
•Port 8
Port 0,3: N-ch open drain
output
•Port 1
•Port 71,72,73
•P70 port input/interrupt
S16 to S51
Port 87 weak signal input
Port 70
Watchdog timer
Output disable
Output disable
Output disable
Output P-channel
Tr. OFF
Output disabled
Output disabled
XT1,XT2,CF1, RES
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
CF1 •CF2 open circuit 4.5 to 6.0
•system clock
divider set to 1/1
•external clock
DUTY = 50±50%
•CF2 open circuit 4.5 to 6.0
•system clock
divider set to 1/2
VSS
VSS
VSS
-35
VSS
VSS
VSS
0.294
0.1
0.2
0.15VDD
+0.4
0.15VDD
+0.4
0.1VDD
+0.4
0.2VDD
0.25VDD
0.8VDD
-1.0
0.25VDD
200
µs
10 MHz
20
Continued
No.6843-11/23

11 Page







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