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PDF LC875148A Data sheet ( Hoja de datos )
| Número de pieza | LC875148A | |
| Descripción | 8-Bit Single Chip Microcontroller with 64/48/32K-Byte ROM and 1024-Byte RAM On Chip | |
| Fabricantes | Sanyo | |
| Logotipo |  |
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Ordering number : ENN*6715
CMOS IC
LC875164A/48A/32A
8-Bit Single Chip Microcontroller with
64/48/32K-Byte ROM and 1024-Byte RAM On Chip
Preliminary
Overview
The LC875164A/48A/32A microcontroller is 8-bit single chip microcontroller with the following on-chip functional blocks:
- CPU: Operable at a minimum bus cycle time of 100ns
- 64K/48K/32K bytes ROM
- 1024 byte RAM
- two high performance 16 bit timer/counters (can be divided into 8 bit units)
- two 8 bit timers with prescalers
- timer for use as date/time clock
- two synchronous serial I/O ports (with automatic block transmit/receive function)
- one asynchronous/synchronous serial I/O port
- 12-bit PWM × 2
- 8-channel × 8-bit AD converter
- high speed 8-bit parallel interface
- 19-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
(1) Read Only Memory
- 65536 × 8 bits (LC875164A)
- 49151 × 8 bits (LC875148A)
- 32512 × 8 bits (LC875132A)
Ver.1.03
O3098
91400 RM (IM) HK / SY No.6715-1/25
1 page  
Pin Assignment
LC875164A/48A/32A
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PB4/D4
PB3/D3
PB2/D2
PB1/D1
PB0/D0
VSS3
VDD3
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
PA0/CS2#
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
LC875164A/48A/32A
QIP80
40 SI2P2/SCK2
39 SI2P1/S12/SB2
38 SI2P0/SO2
37 P17/T1PWMH/BUZ
36 P16/T1PWML
35 P15/SCK1
34 P14/SI1/SB1
33 P13/SO1
32 P12/SCK0
31 P11/SI0/SB0
30 P10/SO0
29 P34
28 P33
27 P32
26 P31
25 P30
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Package Dimension
(unit : mm)
3174
SANYO : QIP-80E
No.6715-5/25
5 Page 
LC875164A/48A/32A
Port Output Configuration
Output configuration and pull-up resistor options are shown in the following table.
Input is possible even when port is set to output mode.
Terminal
Option
applies to:
Option
Output Format
Pull-up resistor
P00-P07
1 bit units
1 CMOS
Programmable (Note 1)
2 Nch-open drain
None
P10-P17
each bit
1 CMOS
Programmable
P20-P27
P30-P34
2 Nch-open drain
Programmable
PA0-PA5
PB0-PB7(*)
PC0-PC7
each bit
1 CMOS
2 Nch-open drain
Programmable
Programmable
P70
-
None
Nch-open drain
Programmable
P71-P73
-
None
CMOS
Programmable
P80-P87
-
None
Nch-open drain
None
SI2P0, SI2P2
-
None
CMOS
None
SI2P3
PWM0,
PWM1
SI2P1
-
None CMOS (When used as standard port)
None
Nch-open drain (When used for SIO2 data)
XT1
-
None
Input only
None
XT2
-
None Output for 32.768kHz crystal oscillation
None
Note 1 Programmable pull-up resisters of Port 0 can be attatched in nibble units (P00-03, P04-07).
(*) When in parallel interface mode, PB0-PB7 output format is CMOS, regardless of any selected option.
Note: Connect as follows to reduce noise on VDD and increase the back-up time.
VSS1, VSS2 and VSS3 must be connected together and grounded.
The voltage of Port 7 should be fixed.
Example 1 : In hold mode, during backup, port output ‘H’ level is supplied from the back-up capacitor.
Power
Supply
Back-up capacitor
LSI
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
Example 2 : During backup in hold mode output is not held high and its value in unsettled.
Power
Supply
Back-up capacitor
LSI
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
No.6715-11/25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet LC875148A.PDF ] | |
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