LC4102C Datasheet PDF - Sanyo
| Part Number | LC4102C | |
| Description | LCD Dot Matrix Common Driver for STN Displays | |
| Manufacturers | Sanyo | |
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Ordering number : EN5789A
CMOS LSI
LC4102C
LCD Dot Matrix Common Driver
for STN Displays
Overview
The LC4102C is a common driver for large-scale dot
matrix LCD panels. It includes a 160-bit bidirectional shift
register and 4-level LCD driver circuits. The number of
bits can be further increased by using the provided input
and output pins to connect multiple LC4102Cs in cascade.
The LC4102C and LC4104C form a large-screen LCD
panel driver chip set.
Features
• Fabricated in a CMOS (P-sub) high-voltage process.
• LCD drive voltage: 36 V
• Logic system power-supply voltage: 2.7 to 5.5 V
• fcp max: 2.5 MHz
• Slim chip (output pads are concentrated on one of the
longer sides)
• Bidirectional shift register
• The shift register can be split into two 80-bit registers.
(Two screens drivable)
• DISPOFF function that locks the drive voltages output
to the LCD at fixed levels.
• Display duty: 1/160 to 1/480
• Appropriate for COG (chip on glass) mounting. (A gold
bump structure is adopted in the pad areas.)
Specifications
The electrical characteristics values shown below are for devices packaged in the Sanyo standard PGA-208 package.
Absolute Maximum Ratings at VSS = 0
Parameter
Symbol
Applicable pins
min typ max Unit
Supply voltage
Input voltage
VDD max
VEE max
VSS max
VIN
V0, V1
V4
V5
VDD
VEE
VSSH
*1
V0, V1 *2
V4 *2
V5 *2
–0.3
–0.3
–0.3
–0.3
VEE – 7.0
–0.3
–0.3
7.0
40.0
0.3
VDD + 0.3
VEE + 0.3
VSS + 7.0
+0.3
V
V
V
V
V
V
V
Operating temperature
Topr
–20 +75 °C
Storage temperature
Tstg
–55
Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO160, DMIN and MODE
2. The voltages V0, V1, V4, and V5 must obey the relationships VEE ≥ V0 ≥ V1 ≥ VEE – 7 V, and 7 V ≥ V4 ≥ V5 ≥ VSSH.
Allowable Operating Ranges at VSS = 0, Ta = –20 to +75°C
+125
°C
Parameter
Symbol
Applicable pins
min typ max Unit
VDD
VDD
2.7 5.5 V
Supply voltage
VEE
VEE
14 36 V
VSSH
VSSH
0V
Input high-level voltage
VIH *1
0.8 × VDD
VDD
V
Input low-level voltage
VIL *1
0
0.2 × VDD
V
V0, V1 V0, V1 *2
VEE – 7.0
VEE V
Input voltage
V4 V4 *2
0
VSSH + 7.0
V
V5 V5 *2
0V
Note: 1. LOAD, RS/LS, DISP, DF, DIO1, DIO160, DMIN and MODE
2. The voltages V0, V1, V4, and V5 must obey the relationships VEE ≥ V0 ≥ V1 ≥ VEE – 7 V, and 7 V ≥ V4 ≥ V5 ≥ VSSH.
When turning on the power supplies, first turn on the logic system power supply and then turn on the high-voltage system power supply; alternatively,
turn both on at the same time.
When turning off the power supplies, first turn off the high-voltage system power supply and then turn off the logic system power supply; alternatively,
turn both off at the same time.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
43098HA (OT)/82097HA (OT) No. 5789-1/8
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Pad Assignment
LC4102C
OUT160
OUT159
OUT2
OUT1
V4
V4
V4
V1 Chip size: 15.75 mm × 1.95 mm
V1
V1
V0
V0
V0
NC
NC
VEE
VEE
VEE
VSSH
VSSH
VSSH
NC
DIO160
NC
NC
DMIN
NC
NC
DIO1
NC
VSS
VSS
VSS
NC
LOAD
NC
VSS
VSS
VSS
NC
DF
NC
NC
DISP
NC
VDD
VDD
VDD
NC
RSLS
NC
NC
MODE
NC
VSSH
VSSH
VSSH
VEE
VEE
VEE
NC
NC
V0
V0
V0
V1
V1
V1
V4
V4
V4
No. 5789-5/8
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| Information | Total 8 Pages | |
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