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PDF K9K4G08U0M Data sheet ( Hoja de datos )
| Número de pieza | K9K4G08U0M | |
| Descripción | 512M x 8 Bit / 256M x 16 Bit NAND Flash Memory | |
| Fabricantes | Samsung | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de K9K4G08U0M (archivo pdf) en la parte inferior de esta página. Total 38 Páginas | ||
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K9W8G08U1M
K9K4G08Q0M K9K4G16Q0M
K9K4G08U0M K9K4G16U0M
FLASH MEMORY
Document Title
512M x 8 Bit / 256M x 16 Bit NAND Flash Memory
Revision History
Revision No History
0.0 1. Initial issue
0.1 1. Add two-K9K4GXXU0M-YCB0/YIB0 Stacked Package
0.2 1. The 3rd Byte ID after 90h ID read command is don’t cared.
The 5th Byte ID after 90h ID read command is deleted.
0.3 1. The K9W8G16U1M-YCB0,YIB0,PCB0,PIB0 is deleted in line up.
2. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
3. Pb-free Package is added.
K9K4G08Q0M-PCB0,PIB0
K9K4G08U0M-PCB0,PIB0
K9K4G16U0M-PCB0,PIB0
K9K4G16Q0M-PCB0,PIB0
K9W8G08U1M-PCB0,PIB0
0.4 1. Added Addressing method for program operation.
0.5 1. The tADL(Address to Data Loading Time) is added.
- tADL Minimum 100ns
- tADL is the time from the WE rising edge of final address cycle
to the WE rising edge of first data cycle at program operation.
2. Added addressing method for program operation
3. PKG(TSOP1) Dimension Change
Draft Date Remark
Feb. 19. 2003 Advance
Mar. 31. 2003 Preliminary
Apr. 9. 2003 Preliminary
Apr. 30. 2003 Preliminary
Jan. 27. 2004 Preliminary
May.31. 2004
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
1 page  
K9W8G08U1M
K9K4G08Q0M K9K4G16Q0M
K9K4G08U0M K9K4G16U0M
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
(K9XXG08XXM)
I/O0 ~ I/O15
(K9K4G16X0M)
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
COMMAND LATCH ENABLE
CLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE / CE1
CHIP ENABLE
The CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is
ignored, and the device does not return to standby mode in program or erase operation. Regarding CE /
CE1 control during read operation, refer to ’Page read’section of Device operation .
CE2
CHIP ENABLE
The CE2 input enables the second K9K4GXXU0M
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
WP The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B1/ R/B2
READY/BUSY OUTPUT
The R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program,
erase or random read operation is in process and returns to high state upon completion. It is an open drain
output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
PRE
POWER-ON READ ENABLE
The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when
PRE pin is tied to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss GROUND
N.C
NO CONNECTION
Lead is not internally connected.
NOTE: Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
5
5 Page 
K9W8G08U1M
K9K4G08Q0M K9K4G16Q0M
K9K4G08U0M K9K4G16U0M
FLASH MEMORY
Program / Erase Characteristics
Parameter
Program Time
Dummy Busy Time for Cache Program
Number of Partial Program Cycles
in the Same Page
Block Erase Time
Main Array
Spare Array
Symbol
tPROG
tCBSY
Nop
tBERS
Min
-
-
-
-
NOTE : 1. Max. time of tCBSY depends on timing between internal program completion and data in
Typ
300
3
-
-
2
Max
700
700
4
4
3
AC Timing Characteristics for Command / Address / Data Input
Parameter
CLE setup Time
CLE Hold Time
CE setup Time
CE Hold Time
WE Pulse Width
ALE setup Time
ALE Hold Time
Data setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
ALE to Data Loading Time
Symbol
tCLS
tCLH
tCS
tCH
tWP
tALS
tALH
tDS
tDH
tWC
tWH
tADL
K9K4G16U0M(3.3V)
K9K4GXXQ0M(1.8V)
Min Max
25 -
10 -
35 -
10 -
25 -
25 -
10 -
20 -
10 -
45 -
15 -
100 -
K9XXG08UXM(3.3V)
Min Max
10 -
5-
15 -
5-
15 -
10 -
5-
10 -
5-
30 -
10 -
100 -
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
Unit
µs
µs
cycles
cycles
ms
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
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| Páginas | Total 38 Páginas | |
| PDF Descargar | [ Datasheet K9K4G08U0M.PDF ] | |
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