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PDF K4D623238B-GC Data sheet ( Hoja de datos )
| Número de pieza | K4D623238B-GC | |
| Descripción | 64Mbit DDR SDRAM | |
| Fabricantes | Samsung | |
| Logotipo |  |
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K4D623238B-GC
64M DDR SDRAM
64Mbit DDR SDRAM
512K x 32Bit x 4 Banks
Double Data Rate Synchronous RAM
with Bi-directional Data Strobe and DLL
(144-Ball FBGA)
Revision 1.4
September 2002
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.4 (Sep. 2002)
1 page  
K4D623238B-GC
64M DDR SDRAM
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
D Q’s and DM’s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQS0 ~ DQS3
Input/Output
Data input and output are synchronized with both edge of DQS.
DQS0 for DQ0 ~ DQ 7, DQS1 for DQ8 ~ DQ15, D Q S2 for DQ16 ~ DQ23,
DQS3 for DQ24 ~ DQ 31.
DM0 ~ DM3
Input
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ 8 ~ DQ 15, DM2 for
D Q16 ~ DQ 23, DM3 for DQ24 ~ DQ 31.
DQ 0 ~ DQ 31
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA0, BA1
Input
Selects which bank is to be active.
A0 ~ A10
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA 10, Column addresses : CA0 ~ CA7.
Column address CA8 is used for auto precharge.
V D D/ V SS
Power Supply
Power and ground for the input buffers and core logic.
V D D Q/ V SSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VREF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
MCL
Must Connect Low
Must connect low
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
-5-
Rev. 1.4 (Sep. 2002)
5 Page 
K4D623238B-GC
64M DDR SDRAM
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, T A=0 to 65°C )
Parameter
Symbol
Test Condition
Version
Unit Note
-33 -40 -45 -50 -55 -60
Operating Current
(One Bank Active)
IC C 1
Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC= tC C(min)
470 340 315 290 275 260 mA 1
Precharge Standby Current
in Power-down mode
IC C 2P
CKE ≤ VIL(max), tCC= tCC(min)
75 65 65 65 65 65 mA
Precharge Standby Current
in Non Power-down mode
IC C 2N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
155 125 120 115 110 105 mA
Active Standby Current
power-down mode
IC C 3P CKE ≤ VIL(max), tCC= tCC(min)
150 130 130 130 130 130 mA
Active Standby Current in
in Non Power-down mode
IC C 3N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
270 220 210 200 190 180 mA
Operating Current
( Burst Mode)
IC C 4
IOL=0mA ,tCC = tCC(min),
Page Burst, All Banks activated.
900 700 650 600 550 520 mA
Refresh Current
Self Refresh Current
IC C 5
IC C 6
tRC ≥ tRFC(min)
CKE ≤ 0.2V
405 340 330 320 310 300 mA
4.5 4 mA
2
3
1 mA 4
Operating Current
( 4Bank Interleaving)
IC C 7
Burst Lenth=4 tRC ≥ tRC(min)
IOL=0mA, tCC= tC C(min)
1050 850 800 750 700 670 mA
Note : 1. Measured with outputs open.
2. Refresh period is 16ms.
3. K4D623238B-GC*
4. K4D623238B-GL*
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, V DD/ VDDQ =2.5V+ 5%, T A=0 to 65°C)
Parameter
Symbol
Min
Typ
Max
Input High (Logic 1) Voltage; DQ
Input Low (Logic 0) Voltage; DQ
VIH VREF +0.35
VIL -
-
-
-
VREF -0.35
Clock Input Differential Voltage; CK and CK
VID
0.7
- VDDQ+0.6
Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*VDDQ +0.2
Unit
V
V
V
V
Note
1
2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
- 11 -
Rev. 1.4 (Sep. 2002)
11 Page | ||
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