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PDF K4D553238F-JC Data sheet ( Hoja de datos )
| Número de pieza | K4D553238F-JC | |
| Descripción | 256Mbit GDDR SDRAM | |
| Fabricantes | Samsung | |
| Logotipo |  |
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K4D553238F-JC
256M GDDR SDRAM
256Mbit GDDR SDRAM
2M x 32Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
with Bi-directional Data Strobe and DLL
(144-Ball FBGA)
Revision 1.0
March 2004
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev 1.0 (Mar. 2004)
1 page  
K4D553238F-JC
256M GDDR SDRAM
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ’s and DM’s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQS0 ~ DQS3
Input/Output
Data input and output are synchronized with both edge of DQS.
DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23,
DQS3 for DQ24 ~ DQ31.
DM0 ~ DM3
Input
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for
DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.
DQ0 ~ DQ31
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA0, BA1
Input
Selects which bank is to be active.
A0 ~ A11
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7,CA9
Column address CA8 is used for auto precharge.
VDD/VSS
Power Supply
Power and ground for the input buffers and core logic.
VDDQ/VSSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VREF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
This pin is recommended to be left "No connection" on the device
Reserved for future use
MCL
Must Connect Low
Must connect low
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
-5-
Rev 1.0 (Mar. 2004)
5 Page 
K4D553238F-JC
256M GDDR SDRAM
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)
Parameter
Symbol
Test Condition
Operating Current
(One Bank Active)
ICC1
Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
Precharge Standby Current
in Power-down mode
ICC2P
CKE ≤ VIL(max), tCC= tCC(min)
Precharge Standby Current
in Non Power-down mode
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
Active Standby Current
power-down mode
ICC3P CKE ≤ VIL(max), tCC= tCC(min)
Active Standby Current in
in Non Power-down mode
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
Operating Current
( Burst Mode)
ICC4
IOL=0mA ,tCC= tCC(min),
Page Burst, All Banks activated.
Refresh Current
ICC5
tRC ≥ tRFC(min)
Self Refresh Current
ICC6
CKE ≤ 0.2V
Operating Current
(4Bank interleaving)
ICC7 Burst Length=4 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
Note : 1. Measured with outputs open.
2. Refresh period is 32ms.
-2A
400
120
190
170
250
650
470
8
840
-33
340
150
130
220
550
415
680
Version
-36
-40
320 300
90
140 130
120 110
210 200
520 460
395 365
6
630 590
Unit Note
-50
280 mA 1
mA
120 mA
100 mA
190 mA
430 mA
335 mA 2
mA
550 mA
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.5V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C)
Parameter
Input High (Logic 1) Voltage; DQ
Input Low (Logic 0) Voltage; DQ
Clock Input Differential Voltage; CK and CK
Symbol
VIH
VIL
VID
Min
VREF+0.35
-
0.7
Typ
-
-
-
Max
-
VREF-0.35
VDDQ+0.6
Unit
V
V
V
Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2
-
0.5*VDDQ+0.2
V
Note
1
2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
- 11 -
Rev 1.0 (Mar. 2004)
11 Page | ||
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