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PDF K4D261638 Data sheet ( Hoja de datos )
| Número de pieza | K4D261638 | |
| Descripción | 128Mbit GDDR SDRAM | |
| Fabricantes | Samsung | |
| Logotipo |  |
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K4D261638F
128M GDDR SDRAM
128Mbit GDDR SDRAM
2M x 16Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
Revision 1.2
January 2004
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.2 (Jan. 2004)
1 page  
K4D261638F
128M GDDR SDRAM
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK, CK*1
CKE
CS
RAS
CAS
WE
LDQS,UDQS
LDM,UDM
DQ0 ~ DQ15
BA0, BA1
A0 ~ A11
VDD/VSS
VDDQ/VSSQ
VREF
NC/RFU
Type
Input
Input
Input
Input
Input
Input
Input/Output
Input
Input/Output
Input
Input
Power Supply
Power Supply
Power Supply
No connection/
Reserved for future use
Function
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ’s and DM’s that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS
corresponds to the data on DQ8-DQ15.
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on
DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA8.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommended to be left "No connection" on the device
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
-5-
Rev. 1.2 (Jan. 2004)
5 Page 
K4D261638F
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)
128M GDDR SDRAM
Parameter
Symbol
Test Condition
Version
Unit Note
-25 -2A -33 -36 -40 -50
Operating Current
(One Bank Active)
ICC1
Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
TBD 210 190 180 170 150 mA 1
Precharge Standby Current
in Power-down mode
ICC2P
CKE ≤ VIL(max), tCC= tCC(min)
TBD
60
45 mA
Precharge Standby Current
in Non Power-down mode
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
TBD
90
75
70
65
60 mA
Active Standby Current
power-down mode
ICC3P CKE ≤ VIL(max), tCC= tCC(min) TBD 75 65 60 55 50 mA
Active Standby Current in
in Non Power-down mode
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
TBD
135
100
100
95
90 mA
Operating Current
( Burst Mode)
ICC4
tRC ≥ tRFC(min)tRC ≥ tRFC(min)
TBD 400 290 275 260 245 mA
Page Burst, All Banks activated.
Refresh Current
ICC5
tRC ≥ tRFC(min)
TBD 245 210 200 195 190 mA 2
Self Refresh Current
ICC6
CKE ≤ 0.2V
4 mA
Note : 1. Measured with outputs open.
2. Refresh period is 32ms.
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.5V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C)
Parameter
Symbol
Min
Typ
Max
Unit
Input High (Logic 1) Voltage; DQ
VIH VREF+0.35
-
-V
Input Low (Logic 0) Voltage; DQ
VIL -
-
VREF-0.35
V
Clock Input Differential Voltage; CK and CK
VID
0.7
-
VDDQ+0.6
V
Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2
-
0.5*VDDQ+0.2
V
Note
1
2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
3. For the K4D261638F-TC25/2A, VDD & VDDQ = 2.8V+0.1V.
- 11 -
Rev. 1.2 (Jan. 2004)
11 Page | ||
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| PDF Descargar | [ Datasheet K4D261638.PDF ] | |
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