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PDF PDSP16330MC Data sheet ( Hoja de datos )

Número de pieza PDSP16330MC
Descripción Pythagoras Processor
Fabricantes Mitel Networks Corporation 
Logotipo Mitel Networks Corporation Logotipo



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No Preview Available ! PDSP16330MC Hoja de datos, Descripción, Manual

Supersedes October 1995 version, DS3240 - 2.1
PDSP16330 MC
Pythagoras Processor
DS3240 - 3.1 November 1998
The PDSP16330 is a high speed digital CMOS IC that
converts Cartesian data (Real and Imaginary) into Polar form
(Magnitude and Phase), at rates up to 10MHz. Cartesian
16+16 bit 2's complement or Sign-Magnitude data is
converted into 16 bit Phase format. The Magnitude output may
be scaled in amplitude by powers of 2. The Phase output
represents a full 2 x π field to eliminate phase ambiguities.
Polyimide is used as an inter-layer dielectric and as
glassivation.
FEATURES
10MHz Cartesian to Polar Conversion
16-Bit Cartesian Inputs
16-Bit Magnitude Output
12-Bit Phase Output
2’s Complement or Sign-Magnitude Input Formats
Three-state Outputs and Independent
Data Enables Simplify System Interfacing
Magnitude Scaling Facility with Overflow Flag
Less than 400 mW Power Dissipation at 10MHz
100 pin CQFP Package
APPLICATIONS
Digital Signal Processing
Digital Radio
Radar Processing
Sonar Processing
Robotics
GC100
Rev
Date
Fig.1 Pin connections - QFP Package
ABC D
FEB 1992 MAR 1993 OCT 1995 NOV 1998
ASSOCIATED PRODUCTS
PDSP16112 16 X 12 Complex Multiplier
PDSP16116 16 X 16 Complex Multiplier
PDSP16318 Complex Accumulator
PDSP16350 I/Q Splitter and NCO
PDSP16510A Stand Alone FFT Processor
ORDERING INFORMATION
PDSP16330/MC/GC1R (10MHz - QFP Package,
MIL-STD-883 Screening)
X15:0
Y15:0
FORM
S0
S1
CEX
2
16
SIGN
MAGNITUDE
15
X2
30
+
32
X2 + Y2
16
SHIFT
CEY
MAGNITUDE
15
Y2
30
SIGN
X>Y
16 16
π
Y/X
9
/4
ARCTAN
ROM
SIGN X SIGN Y
9
ROTATE
12
OEM
OEP
M15:0
OVR
Fig.2 Block diagram
P11:0

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PDSP16330MC pdf
SWITCHING CHARACTERISTICS
PDSP16330 MC
Characteristic
† Input data setup to clock rising edge
† Input data Hold after clock rising edge
† CEX, CEY Setup to clock rising edge
† CEX, CEY Hold aher clock rising edge
† FORM, S1:0 Setup to clock rising edge
† FORM, S1:0 Hold after clock rising edge
† Clock rising edge to valid data
* Clock period
† Clock high time
† Clock low time
† Latency
† OEM, OEP low to data high data valid
† OEM, OEP low to data low data valid
† OEM, OEP high to data high impedance
† OEM, OEP low to data high impedance
† Vcc current (TTL input levels)
† Vcc current (CMOS input levels)
Value
PDSP16330
Min.
Max.
Sub-
Units group
Conditions
15 ns
2 ns
30 ns
0 ns
15 ns
7 ns
5 40 ns
2 x LSTTL + 20pF
100 ns 9,10,11
25 ns
25 ns
24 24 cycles
30 ns
2 x LSTTL + 20pF
30 ns
2 x LSTTL + 20pF
30 ns
2 x LSTTL + 20pF
30 ns
2 x LSTTL + 20pF
110 mA
VCC = Max
Outputs unloaded
Clock freq. = Max
70 mA
VCC = Max
Outputs unloaded
Clock freq. = Max
NOTES
1. LSTTL is equivalent to IOH = 20µA, IOL = -0.4mA
2. Current is defined as negative into the device
3. CMOS input levels are defined as: VIH = VDD - 0.5V, VIL = +0.5V
4. All parameters marked * are tested during production.
Parameters marked † are guaranteed by design and characterisation.
5. All timings are dependent on silicon speed. This speed is tested by measuring clock period.
This guarantees all other timings by characterisation and design.
ABSOLUTE MAXIMUM RATINGS
Supply voltage, Vcc
-0.5V to + 7.0V
Input voltage, VIN
-0.5V to VCC + 0.5V
Output voltage, Vour
-0.5V to VCC + 0.5V
Clamp diode current per pin, IK (see Note 2)
±18mA
Static discharge voltage (HMB), V
500V
STAT
Storage temperature. Tstg
-65°C to + 150°C
Ambient temperature with
power applied Tamb:
Military
-55 °C to + 125 °C
Package power dissipation PTOT
Junction temperature
1200mW
150 °C
THERMAL CHARACTERISTICS
Package Type
GC
θJC°C/W
12
NOTES
1. Exceeding these ratings may cause permanent damage.
Functional operatlon under these conditions is not implied.
2. Maximum dissipation or 1 second should not be exceeded;
only one output to be tested at any one time.
3. Exposure to Absolute Maximum Ratings for extended
periods may affect device reliability
5

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