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PDF M54HC373 Data sheet ( Hoja de datos )
| Número de pieza | M54HC373 | |
| Descripción | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de M54HC373 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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M54/74HC373
M54/74HC533
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT
HC373 NON INVERTING - HC533 INVERTING
. HIGH SPEED
tPD = 11 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH= 6 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS373/533
DESCRIPTION
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC X XX F 1 R
M 74 HC XX XM 1R
M 74HC X XX B1R
M 74H CXX XC 1R
The M54/74HC373/533 are high speed CMOS
OCTAL LATCH WITH 3-STATE OUTPUTS
fabricated with in silicon gate C2MOS technology.
These ICs achive the high speed operation similar
to equivalent LSTTL while maintaning the CMOS
low power dissipation.
of D input data. While the OE input is at low level,
the eight outputs will be in a normal logic state (high
or low logic level) and while high level the outpts will
be in a high impedance state.
The application designer has a choise of
combination of inverting and non inverting outputs.
These 8 bit D-Type latches are controlled by a latch
enable input (LE) and a output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic level
The three state output configuration and the wide
choise of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against discharge and transient excess voltage.
PIN CONNECTION (top view)
HC373
HC533
HC373
HC533
October 1993
1/13
1 page  
M54/M74HC373/533
DC SPECIFICATIONS
Symbol
Parameter
VIH High Level Input
Voltage
VIL Low Level Input
Voltage
VOH High Level
Output Voltage
VOL Low Level Output
Voltage
II Input Leakage
Current
IOZ 3 State Output
Off State Current
ICC Quiescent Supply
Current
Test Conditions
VCC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
VI =
VIH
IO=-20 µA
6.0 or
4.5 VIL IO=-6.0 mA
6.0 IO=-7.8 mA
2.0
4.5
VI =
VIH
IO= 20 µA
6.0 or
4.5 VIL IO= 6.0 mA
6.0 IO= 7.8 mA
6.0 VI = VCC or GND
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
1.5
3.15
4.2
0.5
1.35
1.8
1.9 2.0
4.4 4.5
5.9 6.0
4.18 4.31
5.68 5.8
0.0 0.1
0.0 0.1
0.0 0.1
0.17 0.26
0.18 0.26
±0.1
Value
-40 to 85 oC
74HC
Min. Max.
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
4.13
5.63
0.1
0.1
0.1
0.33
0.33
±1
-55 to 125 oC
54HC
Min. Max.
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
4.10
5.60
0.1
0.1
0.1
0.40
0.40
±1
6.0 VI = VIH or VIL
VO = VCC or GND
6.0 VI = VCC or GND
±0.5 ±5.0 ±10
4 40 80
Unit
V
V
V
V
µA
µA
µA
5/13
5 Page 
DIM.
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
L
M
S
MIN.
0.10
0.35
0.23
12.60
10.00
7.40
0.50
SO20 MECHANICAL DATA
mm
TYP.
0.50
1.27
11.43
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
0.004
0.013
0.009
45° (typ.)
13.00
0.496
10.65
0.393
7.60 0.291
1.27 0.19
0.75
8° (max.)
M54/M74HC373/533
inch
TYP.
0.020
0.050
0.450
MAX.
0.104
0.007
0.096
0.019
0.012
0.512
0.419
0.299
0.050
0.029
P013L
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet M54HC373.PDF ] | |
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