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M54HC280F1R fiches techniques PDF

ST Microelectronics - 9 BIT PARITY GENERATOR

Numéro de référence M54HC280F1R
Description 9 BIT PARITY GENERATOR
Fabricant ST Microelectronics 
Logo ST Microelectronics 





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M54HC280F1R fiche technique
. HIGH SPEED
tPD = 22 ns (TYP.) at VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) at TA = 25 °C 6 V
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH= IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V to 6 V
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS280
M54HC280
M74HC280
9 BIT PARITY GENERATOR
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 28 0F 1R
M 74H C2 80 M1 R
M 74HC 28 0B 1R
M 74H C2 80 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC280 is a high speed CMOS 9-BIT
PARITY GENERATOR fabricated in silicon gate
C2MOS technology. It has the same high speed per-
formance of LSTTL combined with true CMOS low
consumption.
It is composed of nine data inputs (A to I) and
odd/even parity outputs (Σ ODD and Σ EVEN). The
nine data inputs control the output conditions. When
the number of high level inputs is odd, ΣODD output
is kept high and ΣEVEN output low. Conversely,
when the number is even , ΣEVEN output is kept
high and ΣODD low.
This IC generates either odd or even parity making
it flexible application.
The word-length capability is easily expanded by
cascading.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
October 1992
NC =
No Internal
Connection
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