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M54HC175 fiches techniques PDF

ST Microelectronics - QUAD D-TYPE FLIP-FLOP WITH CLEAR

Numéro de référence M54HC175
Description QUAD D-TYPE FLIP-FLOP WITH CLEAR
Fabricant ST Microelectronics 
Logo ST Microelectronics 





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M54HC175 fiche technique
M54HC175
M74HC175
QUAD D-TYPE FLIP-FLOP WITH CLEAR
. HIGH SPEED
tPD = 13 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS175
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 17 5F 1R
M 74H C1 75 M1 R
M 74HC 17 5B 1R
M 74H C1 75 C1 R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC175 is a high speed CMOS QUAD D-
TYPE FLIP-FLOP WITH CLEAR fabricated in sili-
con gate CMOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS low power consumption.
These four flip-flops are controlled by a clock input
(CLOCK) and a clear input (CLEAR). The informa-
tion data applied to the D inputs (1D to 4D) are trans-
fered to the outputs (1Q to 4Q and 1Q to 4Q) on the
positive-going edge of the clock pulse. The reset
function is accomplished when the clear input is
taken low and all Q outputs are kept low regardless
of other input conditions. All inputs are equipped
with protection circuits against static discharge and
transient excess voltage.
October 1992
NC =
No Internal
Connection
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