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PDF M52342FP Data sheet ( Hoja de datos )
| Número de pieza | M52342FP | |
| Descripción | PLL-SPLIT VIF/SIF IC | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI ICs (TV)
M52342FP
PLL-SPLIT VIF/SIF IC
DESCRIPTION
The M52342FP is IF signal-processing IC for VCRs and TVs. It
enable the PLL detection system despite size as small as that of
conventional quasi-synchronous VIF/SIF detector, IF/RF AGC, SIF
limiter, FM detector, QIF AGC and EQ AMP.
FEATURES
• Video detection output is 2VP-P. It has built-in EQ AMP.
• The package is a 24-pin flat package, suitable for space saving.
• The video detector uses PLL for full synchronous detection
circuit. It produces excellent characteristics of DG, DP, 920kHz
beat, and cross color.
• Dynamic AGC realizes high speed response with only single
filter.
• Video IF and sound IF signal processings are separated from
each other. VCO output is used to obtain intercarrier. This PLL-
SPLIT method and built-in QIF AGC provide good sound
sensitivity and reduces buzz.
• As AFT output voltage uses the APC output voltage, VCO coil is
not used.
• Audio FM demodulation uses PLL system, so it has wide
frequency range with no external parts and no adjustment.
APPLICATION
TV sets, VCR tuners
RECOMMENDED OPERATING CONDITION
In case of VCC and Vreg. out short
Supply voltage range....................................................4.75 to 5.25V
Recommended supply voltage...................................................5.0V
Incase of Vreg. out open
Supply voltage range......................................................8.5 to 12.5V
PIN CONFIGURATION (TOP VIEW)
RF AGC DELAY 1
AFT OUT 2
RF AGC OUT 3
VIF IN 4
VIF IN 5
GND 6
GND 7
GND 8
QIF DET IN 9
IF AGC FILTER 10
NFB 11
AUDIO OUT 12
24 EQ F/B
23 APC FILTER
22 VIDEO OUT
21 Vreg. OUT
20 Vreg. OUT
19 VCO COIL
18 VCO COIL
17 Vcc
16 Vcc
15 QIF OUT
14 AFT SW/NPSW
13 LIMITER IN
Outline 24P2N-A
BLOCK DIAGRAM
APC FILTER
Vreg. OUT
VCO COIL
EQ F/B
VIDEO OUT
Vreg. OUT
VCO COIL
24 23 22 21 20 19 18
Vcc
17
QIF OUT
LIMITER IN
Vcc AFT SW/NPSW
16 15 14 13
VCO
Vcc REG
Inter
Split
LIM AMP
AFT
EQ
AMP
VIDEO
DET
APC
QIF DET
QIF AGC
QIF AMP
FM DET
VIF AMP
RF AGC
IF AGC
AF AMP
1234
RF AGC DELAY
RF AGC OUT
AFT OUT
VIF IN
5
VIF IN
6
GND
7
GND
8
GND
9 10 11
IF AGC FILTER
QIF DET IN
NFB
12
AUDIO OUT
1
1 page  
MITSUBISHI ICs (TV)
M52342FP
PLL-SPLIT VIF/SIF IC
3. IN the graph, maximum and minimum DC voltage are V2H and
V2L, respectively.
TP2
Voltage
3V
V2H
2V
V2L
f (3) f (2) f (MHz)
1000 (mV)
µ=
f (2) - f (3) (kHz)
(mV/kHz)
IM Intermodulation
1. Input SG11 into VIF IN, and measure EQ output TP18A with an
oscilloscope.
2. Adjust AGC filter voltage V8 so that the minimum DC level of the
output waveform is 1.0V.
3. At this time, measure, TP18A with a spectrum analyzer.
The intermodulation is defined as a difference between 920kHz
and 3.58MHz frequency components.
LIM Limiting sensitivity
1. Input SG17 (SG22) into SIF input, and measure the 400Hz
component level of AF output TP10.
2. Input SG19 (SG24) into SIF input, and measure the 400Hz
component level of AF output TP10.
3. The input limiting sensitivity is defined as the input level when a
difference between each 400Hz components of audio output
(TP10) is 30dB, as shown below.
Audio output
(mVrms)
30dB
Audio output while
SG17 (SG22) is input
Audio output while
SG19 (SG24) is input
AF S/N
1. Input SG20 (SG25) into SIF input, and measure the output noise
level of AF output TP1. This level is named VN.
2. S/N is;
VoAF (mVr.m.s)
S/N=20log VN (mVr.m.s) (dB)
CQIF QIF control
Lower the voltage of V7, and measure the voltage of V7 when DC
voltage of TP13 begins to change.
THE NOTE IN THE SYSTEM SETUP
M52342FP has 2 power supply pins of Vcc (pin 14) and Vreg. OUT
(pin 17). Pin 14 is for AFT output, RF AGC output circuits and 5V
regulated power circuit and Pin 17 is for the other circuit blocks.
In case M52342FP is used together with other ICs like VIF
operating at more than 5V, the same supply voltage as that of
connected ICs is applied to VCC and Vreg. Out is opened. The other
circuit blocks, connected to Vreg. OUT are powered by internal 5V
regulated power supply.
In case the connecting ICs are operated at 5V, 5V is supplied to
both VCC and Vreg.OUT.
LOGIC TABLE
10k “H”
10k “L”
20k “H”
20k “L”
20k “H”
20k “L”
AF
NTSC
PAL
AFT
DEFEAT
NORMAL
DEFEAT
NORMAL
(dBµ) SIF input
AMR AM Rejection
1. Input SG18 (SG23) into SIF input, and measure the output level
of AF output TP10. This level is named VAM.
2. AMR is;
VoAF (mVr.m.s)
AMR=20log
(dB)
VAM (mVr.m.s)
5
5 Page 
Pin 15 (QIF OUTPUT / INTER OUTPUT)
Drive current
: 0.5mA
terminal voltage : 2.45V
15
MITSUBISHI ICs (TV)
M52342FP
PLL-SPLIT VIF/SIF IC
In both the split and intercarrier system, the carrier signal
to SIF provided from pin 15 through an emitter follower.
Pin 16, Pin 17 (VCC)
VCC
16
17
The recommended supply voltage is 5V or 9 to 12V.
In the case of 5V supply, these pins should be tied to pin 20
and pin 21.
In the case of 9 to 12V supply, a regulated output of 5V
are available in pin 20 and 21.
Pin 18, Pin 19 (VCO COIL)
850Ω
850Ω
466Ω
18
19
466Ω
Connecting a tuning coil and capacitor to these pins enables
an oscillation.
The tuning capacitor of about 30pF is recommended.
The oscillation frequency is tuned in f0.
In the actual adjustment, the coil is tuned so that the AFT
voltage is reached to Vcc/2 with f0 as an input.
The printed pattern around these pins should be designed
carefully to prevent an pull-in error of VCO, caused by the leakage
interference from the large signal level oscillator to adjacent pins.
The interconnection also should be designed as short as possible.
Pin 20, Pin 21 (REG OUTPUT)
21
20
12.1kΩ
3.8kΩ
It is a regulated 5V output which has current drive
capability of approximately 15mA.
11
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