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PDF PDI1394P11 Data sheet ( Hoja de datos )
| Número de pieza | PDI1394P11 | |
| Descripción | 3-port physical layer interface | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
PDI1394P11
3-port physical layer interface
Product specification
Supersedes data of 1998 Sep 24
1999 Apr 09
Philips
Semiconductors
1 page  
Philips Semiconductors
3-port physical layer interface
Product specification
PDI1394P11
associated link controller. The received data is also transmitted out
the other active cable ports.
The cable status, bus initialization and arbitration states are
monitored through the cable interface using differential comparators.
The outputs of these comparators are used by internal logic to
determine cable and arbitration status. The TPA channel monitors
the incoming cable common-mode voltage value during arbitration to
determine the speed of the next packet transmission. The TPB
channel monitors the incoming cable common-mode voltage for the
presence of the remotely supplied twisted-pair bias voltage,
indicating the cable connection status.
The PDI1394P11 provides a nominal 1.85 V for driver load
termination. This bias voltage, when seen through a cable by a
remote receiver, is used to sense the presence of an active
connection. The value of this bias voltage has been chosen to allow
inter-operability between transceiver chips operating from either 5 V
nominal supplies, or 3.3 V nominal supplies. This bias voltage
source should be stabilized by using an external filter capacitor.
8.0 RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITION
VDD
VIH
VIL
VID–100
VID–200
VID–ARB
DC supply voltage
High level input voltage
Low level input voltage
Differential input voltage
Differential input voltage
Differential input voltage
VIC–100 Common mode voltage
VIC–200SP Common mode voltage
Receive input jitter
Receive input skew
IOL/IOH Output current, IOL/IOH
IO
fXTAL
Tamb
Output current
Crystal frequency
Operating ambient
temperature range in free air
Source/non-source power node
CMOS inputs
CMOS inputs
Cable inputs, 100Mbit operation
Cable inputs, 200Mbit operation
Cable inputs, during arbitration
TPB cable inputs, 100Mbit or speed signaling OFF,
source power node
TPB cable inputs, 100Mbit or speed signaling OFF,
non–source power node
TPB cable inputs, 200Mbit or speed signaling,
source power node
TPB cable inputs, 200Mbit or speed signaling,
non–source power node
TPA, TPB cable inputs, 100Mbit operation
TPA, TPB cable inputs, 200Mbit operation
Between TPA and TPB cable inputs, 100Mbit
operation
Between TPA and TPB cable inputs, 200Mbit
operation
SYSCLK
Control, Data, CNA, C/LKON
TPBIAS outputs
Parallel resonant fundamental mode crystal
MIN
3.0
2.0
142
132
171
1.165
LIMITS
TYP
3.3
MAX
3.6
5.5
0.8
260
260
262
2.515
1.165
2.015
0.935
2.515
0.935
2.015
±1.08
±0.5
±0.8
±0.55
–16
–12
–3
24.5735
24.576
16
12
1.3
24.5785
0 +70
UNIT
V
V
V
mV
mV
mV
V
V
ns
ns
ns
ns
mA
mA
MHz
°C
1999 Apr 09
5
5 Page 
Philips Semiconductors
3-port physical layer interface
Product specification
PDI1394P11
17.1 Arbitrated (short) Bus Reset
A 1394-1995 software initiated bus reset assumes that the state of
the bus is unknown when reset occurs and requires that the reset be
long enough to permit the longest transaction to finish and still
complete reset (167µs min. to 250µs max.). The total duration of bus
initialization is longer than the nominal isochronous cycle time
(125µs) and may disrupt two isochronous periods. This compels
device designers to add additional buffer depth to preserve the
smooth flow of isochronous data from the perspective of their
application. If a node that initiates a reset arbitrates for control of the
bus prior to asserting reset, arbitration time can be shortened
significantly (1.3µs min. to 80µs max.). This 1394a concept is known
as Arbitrated (short) Bus Reset, and is incorporated in the
PDI1394P11.
The TESTM2 (pin 21) pins is used to enable Arbitrated (short) Bus
Reset mode. In 1394-1995 mode, this pin is tied high. In this mode,
an arbitrated bus reset cannot be initiated from this node and will be
treated as a “long” bus reset if initiated by another node. In
accordance with the 1394-1995 spec, all bus resets on the entire
bus will be “long”.
To enable Arbitrated (short) Bus Reset mode, set TESTM2 low.
With the part in this mode, writing a 1 to the ISBR (Initiate Short Bus
Reset) bit (bit 7) of Phy register 9 initiates an arbitrated bus reset.
This mode also allows the Phy to recognize arbitrated bus resets
initiated by other nodes. Non-arbitrated bus resets can still be
initiated from this node and are recognized and processed correctly
when initiated by another node.
17.2 Setting the CPS Trip Point
The Cable Power Status (CPS) pin (pin 23) is used to monitor the
cable power. When cable power voltage has dropped too low for
reliable operation, internal circuitry trips, which clears the CPS bits
in the Phy registers (bit 7 of register 0, and bit 2 of register 6). This
action causes a cable power status interrupt which sets the CPSint
bit in the Phy registers (bit 1 of register 6). This bit can be cleared by
a hardware reset or by writing a 0 to the CPSint bit. However, if the
CPS input is still low, another cable-power status interrupt
immediately occurs. The cable voltage at which these events occur
is adjustable on the PDI1394P11.
The external resistor (R) needed to set the CPS trip voltage (Vcable)
to a desired voltage can be calculated using the following equation:
R
+
(Vcable * 1.85V)
10mA
The external and internal circuitry associated with the CPS pin is
illustrated in Figure 5.
Vcable
R
CPS
COMPARATOR
Icomp
10µA
Vcomp
1.85V
Figure 5.
Phy
SV00921
Some typical threshold voltage values and their associated resistor
values are shown in Table 1.
Table 1. Typical threshold voltage values
Vcable (V)
R (kΩ)
Vcable DETECTOR
TOLERANCE % WITH:
R of 5%
R of 2%
5 315
6.8
4.4
6 415
7.3
4.8
7 515
7.8
5.2
8 615
8.3
5.6
9 715
8.8
6.0
1999 Apr 09
11
11 Page | ||
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| PDF Descargar | [ Datasheet PDI1394P11.PDF ] | |
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