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M54HC137 Datasheet دیتاشیت PDF دانلود

دیتاشیت - ST Microelectronics - 3 TO 8 LINE DECODER/LATCH INVERTING

شماره قطعه M54HC137
شرح مفصل 3 TO 8 LINE DECODER/LATCH INVERTING
تولید کننده ST Microelectronics 
آرم ST Microelectronics 


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M54HC137 شرح
M54HC137
M74HC137
3 TO 8 LINE DECODER/LATCH (INVERTING)
. HIGH SPEED
tPD = 11 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH= IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS137
DESCRIPTION
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 13 7F 1R
M 74H C1 37 M1 R
M 74HC 13 7B 1R
M 74H C1 37 C1 R
The M54/74HC137 is a high speed CMOS 3 TO 8LINE
DECODER/LATCH (INVERTING) fabricated in silicon
gate C2MOS technology. It has the same high speed
performance of LSTTL combined with true CMOS low
power consumption. This device is a 3 to 8line decoder
withlatches on thethree address inputs. When GL goes
from low tohigh, theaddress present at theselect inputs
(A, B and C) is stored in the latches. As long as GL re-
mains high no address changes will be recognized. Out-
put enable pins G1 and G2, control the state of the
outputs independently of the select or latch-enable in-
puts. All the outputs are high unless G1 is high and G2
is low. The HC137 is ideally suited for the implementa-
tion of glitch-free decoders in stored-address applica-
tions in bus oriented systems. All inputs are equipped
withprotection circuits against staticdischarge and tran-
sient excess voltage.
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
February 1993
NC =
No Internal
Connection
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