|
|
PDF EDI88512CA Data sheet ( Hoja de datos )
| Número de pieza | EDI88512CA | |
| Descripción | 512Kx8 Monolithic SRAM/ SMD 5962-95600 | |
| Fabricantes | ETC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de EDI88512CA (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
■ Access Times of 15, 17, 20, 25, 35, 45, 55ns
■ Data Retention Function (LPA version)
■ TTL Compatible Inputs and Outputs
■ Fully Static, No Clocks
■ Organized as 512Kx8
■ Commercial, Industrial and Military Temperature Ranges
■ 32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic Sidebrazed 400 mil DIP (Package 326)
• Ceramic 32 pin Flatpack (Package 344)
• Ceramic Thin Flatpack (Package 321)
• Ceramic SOJ (Package 140)
■ 36 lead JEDEC Approved Revolutionary Pinout
• Ceramic Flatpack (Package 316)
• Ceramic SOJ (Package 327)
• Ceramic LCC (Package 502)
■ Single +5V (±10%) Supply Operation
The EDI88512CA is a 4 megabit Monolithic CMOS
Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolu-
tionary standard for the four megabit device. All 32 pin
packages are pin for pin upgrades for the single chip
enable 128K x 8, the EDI88128CS. Pins 1 and 30 be-
come the higher order addresses.
The 36 pin revolutionary pinout also adheres to the
JEDEC standard for the four megabit device. The cen-
ter pin power and ground pins help to reduce noise in
high performance systems. The 36 pin pinout also
allows the user an upgrade path to the future 2Mx8.
A Low Power version with Data Retention
(EDI88512LPA) is also available for battery backed
applications. Military product is available compliant to
Appendix A of MIL-PRF-38535.
FIG. 1 PIN CONFIGURATION
36 PIN
TOP VIEW
32 PIN
TOP VIEW
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
VSS 16
32 VCC
31 A15
30 A17
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
PIN DESCRIPTION
I/O0-7 Data Inputs/Outputs
A0-18 Address Inputs
WE Write Enables
CS Chip Selects
OE Output Enable
VCC Power (+5V ±10%)
VSS Ground
NC Not Connected
BLOCK DIAGRAM
Memory Array
A -18
Address
Buffer
Address
Decoder
I/O
Circuits
I/O -7
Aug. 2002 Rev. 9
WE
CS
OE
1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
1 page  
EDI88512CA
DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY)
(TA = -55°C TO +125°C)
Characteristic
Low Power Version only
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time
Operation Recovery Time
Sym
VDD
ICCDR
TCDR
TR
Conditions
VDD = 2.0V
CS ³ VDD -0.2V
VIN ³ VDD -0.2V
or VIN £ 0.2V
Min
2
–
0
TAVAV
Typ
–
–
–
–
Max Units
–V
2 mA
– ns
– ns
FIG. 5 DATA RETENTION - CS CONTROLLED
WS32K32-XHXDATA RETENTION MODE
VCC
4.5V
VDD 4.5V
tCDR
tR
CS CS = VDD -0.2V
DATA RETENTION, CS CONTROLLED
5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet EDI88512CA.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| EDI88512C | 512Kx8 Monolithic SRAM |  Microsemi |
| EDI88512CA | 512Kx8 Monolithic SRAM/ SMD 5962-95600 | ETC |
| EDI88512CA | 512Kx8 Monolithic SRAM | Microsemi |
| EDI88512CA-XMXG | 512Kx8 Plastic Monolithic SRAM CMOS | Microsemi |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |