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PDF EDE5104GBSA Data sheet ( Hoja de datos )
| Número de pieza | EDE5104GBSA | |
| Descripción | 512M bits DDR-II SDRAM | |
| Fabricantes | Elpida Memory | |
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PRELIMINARY DATA SHEET
512M bits DDR-II SDRAM
EDE5104GBSA (128M words × 4 bits)
EDE5108GBSA (64M words × 8 bits)
EDE5116GBSA (32M words × 16 bits)
Description
The EDE5104GB is a 512M bits DDR-II SDRAM
organized as 33,554,432 words × 4 bits × 4 banks.
The EDE5108GB is a 512M bits DDR-II SDRAM
organized as 16,777,216 words × 8 bits × 4 banks.
It packaged in 64-ball µBGA package.
The EDE5116GB is a 512M bits DDR-II SDRAM
organized as 8,388,608 words × 16 bits × 4 banks.
It is packaged in 84-ball µBGA package.
Features
• 1.8V power supply
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• 7.8µs average periodic refresh interval
• 1.8V (SSTL_18 compatible) I/O
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
• /DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
• µBGA package is lead free solder (Sn-Ag-Cu)
Document No. E0249E30 (Ver. 3.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
1 page  
EDE5104GBSA, EDE5108GBSA, EDE5116GBSA
Electrical Specifications
• All voltages are referenced to VSS (GND)
• Execute power-up and Initialization sequence before proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit Note
Power supply voltage
VDD
–0.5 to +2.3
V1
Power supply voltage for output
VDDQ
–0.5 to +2.3
V1
Input voltage
VIN –0.5 to +2.3
V1
Output voltage
VOUT
–0.5 to +2.3
V1
Operating temperature (ambient)
TA
0 to +70
°C 1
Storage temperature
TSTG
–55 to +150
°C 1
Power dissipation
PD 1.0
W1
Short circuit output current
IOUT
50
mA 1
Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (SSTL_18)
• There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all
conditions VDDQ must be less than or equal to VDD.
Parameter
Symbol
min.
Typ. max.
Unit Notes
Supply voltage
VDD
1.7
1.8 1.9
V4
Supply voltage for output
VDDQ
1.7
1.8 1.9
V4
Input reference voltage
VREF
0.49 × VDDQ
0.50 × VDDQ 0.51 × VDDQ
V
1, 2
Termination voltage
VTT
VREF – 0.04
VREF
VREF + 0.04
V
3
DC input logic high
VIH (dc)
VREF + 0.125
VDDQ + 0.3V V
DC input low
VIL (dc)
–0.3
VREF – 0.125 V
AC input logic high
VIH (ac)
VREF + 0.250
V
AC input low
VIL (ac)
VREF – 0.250 V
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically
the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected
to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed ±2% VREF (dc).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and
VDDL tied together.
Preliminary Data Sheet E0249E30 (Ver. 3.0)
5
5 Page 
EDE5104GBSA, EDE5108GBSA, EDE5116GBSA
Pin Function
CK, /CK (input pins)
CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK
(both directions of crossing).
/CS (input pin)
All commands are masked when /CS is registered High. /CS provides for external bank selection on systems with
multiple banks. /CS is considered part of the command code.
/RAS, /CAS, /WE (input pins)
/RAS, /CAS and /WE (along with /CS) define the command being entered.
A0 to A13 (input pins)
Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write
commands to select one location out of the memory array in the respective bank.
[Address Pins Table]
Address (A0 to A13)
Part number
Row address
EDE5104GB
AX0 to AX13
EDE5108GB
AX0 to AX13
EDE5116GB
AX0 to AX12
Notes: 1. A13 pin is NC for ×16 organization.
Column address
AY0 to AY9, AY11
AY0 to AY9
AY0 to AY9
Notes
1
A10 (AP) (input pin)
A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = Low)
or all banks (A10 = High). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address
inputs also provide the op-code during mode register set commands.
BA0, BA1 (input pins)
BA0 and BA1 define to which bank an active, read, write or precharge command is being applied. BA0 also
determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.
[Bank Select Signal Table]
Bank 0
Bank 1
Bank 2
Bank 3
Remark: H: VIH. L: VIL.
BA0
L
H
L
H
BA1
L
L
H
H
CKE (input pin)
CKE High activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers.
Taking CKE Low provides precharge power-down and Self Refresh operation (all banks idle), or active power-down
(row active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is
asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self
refresh.
Preliminary Data Sheet E0249E30 (Ver. 3.0)
11
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