|
|
PDF ICL7109 Data sheet ( Hoja de datos )
| Número de pieza | ICL7109 | |
| Descripción | 12-Bit/ Microprocessor- Compatible A/D Converter | |
| Fabricantes | Intersil | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICL7109 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
November 2000
Features
®
FcO1o-R8n8tAa8c-PItNOOoTSBuESSrRIOTBSeLLIcLEEhTonSEriUcwPaBRwlSSOwTuDI.TipnUUptCeoTrTrEst iPCl.RceonOmtDe/rUtsaCctT
Description
ICL7109
12-Bit, Microprocessor-
Compatible A/D Converter
• 12-Bit Binary (Plus Polarity and Over-Range) Dual
Slope Integrating Analog-to-Digital Converter
• Byte-Organized, TTL Compatible Three-State Outputs
and UART Handshake Mode for Simple Parallel or
Serial Interfacing to Microprocessor Systems
• RUN/HOLD Input and STATUS Output Can Be Used to
Monitor and Control Conversion Timing
• True Differential Input and Differential Reference
• Low Noise (Typ) . . . . . . . . . . . . . . . . . . . . . . . . 15µVP-P
• Input Current (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . .1pA
• Operates At Up to 30 Conversions/s
• On-Chip Oscillator Operates with Inexpensive 3.58MHz
TV Crystal Giving 7.5 Conversions/s for 60Hz Rejec-
tion. May Also Be Used with An RC Network Oscillator
for Other Clock Frequencies
The ICL7109 is a high performance, CMOS, low power
integrating A/D converter designed to easily interface with
microprocessors.
The output data (12 bits, polarity and over-range) may be
directly accessed under control of two byte enable inputs and a
chip select input for a single parallel bus interface. A UART
handshake mode is provided to allow the ICL7109 to work with
industry-standard UARTs in providing serial data transmission.
The RUN/HOLD input and STATUS output allow monitoring
and control of conversion timing.
The ICL7109 provides the user with the high accuracy, low
noise, low drift versatility and economy of the dual-slope
integrating A/D converter. Features like true differential input
and reference, drift of less than 1µV/oC, maximum input bias
current of 10pA, and typical power consumption of 20mW
make the ICL7109 an attractive per-channel alternative to
analog multiplexing for many data acquisition applications.
Part Number Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
ICL7109MDL
-55 to 125 40 Ld SBDIP
ICL7109IDL
-25 to 85 40 Ld SBDIP
ICL7109IJL
-25 to 85 40 Ld CERDIP
ICL7109CPL
0 to 70 40 Ld PDIP
ICL7109MDL/883B -55 to 125 40 Ld SBDIP
ICL7109IPL
-25 to 85 40 Ld PDIP
PKG.
NO.
D40.6
D40.6
F40.6
E40.6
D40.6
E40.6
Pinout
ICL7109
(CERDIP, PDIP, SBDIP)
TOP VIEW
GND 1
STATUS 2
POL 3
OR 4
B12 5
B11 6
B10 7
B9 8
B8 9
B7 10
B6 11
B5 12
B4 13
B3 14
B2 15
B1 16
TEST 17
LBEN 18
HBEN 19
CE/LOAD 20
40 V+
39 REF IN -
38 REF CAP-
37 REF CAP+
36 REF IN+
35 IN HI
34 IN LO
33 COMMON
32 INT
31 AZ
30 BUF
29 REF OUT
28 V-
27 SEND
26 RUN/HOLD
25 BUF OSC OUT
24 OSC SEL
23 OSC OUT
22 OSC IN
21 MODE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
File Number 3092.2
1 page  
ICL7109
Pin Descriptions (Continued)
PIN SYMBOL
DESCRIPTION
24
OSC SEL
Oscillator Select - Input high configures OSC IN, OSC OUT, BUF OSC OUT as RC oscillator - clock
will be same phase and duty cycle as BUF OSC OUT.
Input low configures OSC IN, OSC OUT for crystal oscillator - clock frequency will be 1/58 of
frequency at BUF OSC OUT.
25 BUF OSC OUT Buffered Oscillator Output
26
RUN/HOLD
Input High - Conversions continuously performed every 8192 clock pulses.
Input Low - Conversion in progress completed, converter will stop in Auto-Zero 7 counts before
integrate.
27
SEND
Input - Used in handshake mode to indicate ability of an external device to accept data. Connect to
+5V if not used.
28 V- Analog Negative Supply - Nominally -5V with respect to GND (Pin 1).
29
REF OUT
Reference Voltage Output - Nominally 2.8V down from V+ (Pin 40).
30
BUFFER
Buffer Amplifier Output.
31 AUTO-ZERO Auto-Zero Node - Inside foil of CAZ .
32 INTEGRATOR Integrator Output - Outside foil of CINT.
33
COMMON
Analog Common - System is Auto-Zeroed to COMMON.
34
INPUT LO
Differential Input Low Side.
35
INPUT HI
Differential Input High Side.
36
REF IN +
Differential Reference Input Positive.
37
REF CAP +
Reference Capacitor Positive.
38
REF CAP-
Reference Capacitor Negative.
39
REF IN-
Differential Reference Input Negative.
40 V+ Positive Supply Voltage - Nominally +5V with respect to GND (Pin 1).
NOTE: All digital levels are positive true.
5
5 Page 
ICL7109
Reference Voltage
The analog input required to generate a full scale output of
4096 counts is VIN = 2VREF . For normalized scale, a refer-
ence of 2.048V should be used for a 4.096V full scale, and
204.8mV should be used for a 0.4096V full scale. However,
in many applications where the A/D is sensing the output of
a transducer, there will exist a scale factor other than unity
between the absolute output voltage to be measured and a
desired digital output. For instance, in a weighing system,
the designer might like to have a full scale reading when the
voltage from the transducer is 0.682V. Instead of driving the
input down to 409.6mV, the input voltage should be mea-
sured directly and a reference voltage of 0.341V should be
used. Suitable values for integrating resistor and capacitor
are 33kΩ and 0.15µF. This avoids a divider on the input.
Another advantage of this system occurs when a zero read-
ing is desired for non-zero input. Temperature and weight
measurements with an offset or tare are examples. The off-
set may be introduced by connecting the voltage output of
the transducer between common and analog high, and the
offset voltage between common and analog low, observing
polarities carefully. However, in processor-based systems
using the ICL7109, it may be more efficient to perform this
type of scaling or tare subtraction digitally using software.
Reference Sources
The stability of the reference voltage is a major factor in the
overall absolute accuracy of the converter. The resolution of
the ICL7109 at 12 bits is one part in 4096, or 244ppm. Thus
if the reference has a temperature coefficient of 80ppm/oC
(onboard reference) a temperature difference of 3oC will
introduce a one-bit absolute error.
For this reason, it is recommended that an external high-
quality reference be used where the ambient temperature is
not controlled or where high-accuracy absolute measure-
ments are being made.
The ICL7109 provides a REFerence OUTput (Pin 29) which
may be used with a resistive divider to generate a suitable
reference voltage. This output will sink up to about 20mA
without significant variation in output voltage, and is provided
with a pullup bias device which sources about 10µA. The
output voltage is nominally 2.8V below V+, and has a tem-
perature coefficient of ±80ppm/oC (Typ). When using the
onboard reference, REF OUT (Pin 29) should be connected
to REF- (Pin 39), and REF+ should be connected to the
wiper of a precision potentiometer between REF OUT and
V+. The circuit for a 204.8mV reference is shown in the test
circuit. For a 2.048mV reference, the fixed resistor should be
removed, and a 25kΩ precision potentiometer between REF
OUT and V+ should be used.
Note that if Pins 29 and 39 are tied together and Pins 39 and
40 accidentally shorted (e.g., during testing), the reference
supply will sink enough current to destroy the device. This can
be avoided by placing a 1kΩ resistor in series with Pin 39.
Detailed Description
Digital Section
The digital section includes the clock oscillator and scaling
circuit, a 12-bit binary counter with output latches and TTL-
compatible three-state output drivers, polarity, over-range
and control logic, and UART handshake logic, as shown in
Figure 4.
Throughout this description, logic levels will be referred to as
“low” or “high”. The actual logic levels are defined in the Elec-
trical Specifications Table. For minimum power consumption,
all inputs should swing from GND (low) to V+ (high). Inputs
driven from TTL gates should have 3-5kΩ pullup resistors
INTEGRATOR
OUTPUT
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
AZ PHASE I
2048 COUNTS
MINIMUM
POLARITY
DETECTED
INT PHASE II
FIXED 2048
COUNTS
NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO VIN
ZERO CROSSING
OCCURS
ZERO CROSSING
DETECTED
DEINT PHASE III
AZ
4096 COUNTS
MAX
AFTER ZERO CROSSING
ANALOG SECTION WILL
BE IN AUTOZERO
CONFIGURATION
MODE Input
FIGURE 3. CONVERSION TIMING (RUN/HOLD PIN HIGH)
The MODE input is used to control the output mode of the
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ICL7109.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICL7101 | (ICL7101 / ICL8052) 3 1/2 Digital A/D |  Intersil Corporation |
| ICL7103 | (ICL7103 / ICL8052 / ICL8068) Precision 4 1/2 Digit A/D Converter | Intersil |
| ICL7104 | 14-Bit/16-Bit/ Microprocessor- Compatible/ 2-Chip/ A/D Converter | Intersil |
| ICL7106 | 31/2 Digit/ LCD/LED Display/ A/D Converters | Intersil |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |