PDF HYM72V1645GU-60 Data sheet ( Hoja de datos )

Número de pieza	HYM72V1645GU-60
Descripción	3.3V 16M x 64-Bit EDO-DRAM Module 3.3V 16M x 72-Bit EDO-DRAM Module
Fabricantes	Siemens
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No Preview Available ! 3.3V 16M × 64-Bit EDO-DRAM Module 3.3V 16M x 72-Bit EDO-DRAM Module 168pin unbuffered DIMM Module with serial presence detect HYM64V1605GU-50/-60 HYM64V1645GU-50/-60 HYM72V1605GU-50/-60 HYM72V1645GU-50/-60 • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module for PC main memory applications • 1 bank 16M x 64, 16M x 72 in 4k and 8k refresh organisations • Optimized for byte-write non-parity or ECC applications • Extended Data Out (EDO) • Performance: tRAC tCAC tAA tRC tHPC RAS Access Time CAS Access Time Access Time from Address Cycle Time EDO Mode Cycle Time -50 50 ns 13 ns 25 ns 84 ns 20 ns -60 60 ns 15 ns 30 ns 104 ns 25 ns • Single +3.3 V ± 0.3 V Power Supply • CAS-before-RAS refresh, RAS-only-refresh • Decoupling capacitors mounted on substrate • All inputs, outputs and clocks are fully LV-TTL compatible • Serial presence detects (optional) • Utilizes 16M x 4 -DRAMs in TSOPII packages • 4096 refresh cycles / 64 ms with 12 / 12 addressing ( Row / Column) for HYM64/72V1605GU • 8192 refresh cycles / 128 ms with 13 / 11 addressing ( Row / Column) for HYM64/72V1645GU • Gold contact pads • Card Size: 133,35mm x 32,00 mm x 4,00 mm • This DRAM product module family is intended to be fully pin and architecture compatible with the 168pin unbuffered SDRAM DIMM module family Semiconductor Group 1 2.97 1 page HYM 64(72)V1605/45GU-50/-60 16M x 64/72 DRAM Module RAS0 WE0 OE0 CAS0 DQ0-DQ3 I/O1-I/O4 D0 RAS2 WE2 OE2 CAS4 DQ32-DQ35 I/O1-I/O4 D8 DQ4-DQ7 CAS1 DQ8-DQ11 I/O1-I/O4 D1 I/O1-I/O4 D2 D36-DQ39 CAS5 DQ40-DQ43 I/O1-I/O4 D9 I/O1-I/O4 D10 DQ12-DQ15 CAS2 DQ16-DQ19 I/O1-I/O4 D3 I/O1-I/O4 D4 DQ44-DQ47 CAS6 DQ48-DQ51 I/O1-I/O4 D11 I/O1-I/O4 D12 D20-DQ23 CAS3 DQ24-DQ27 I/O1-I/O4 D5 I/O1-I/O4 D6 DQ52-DQ55 CAS7 DQ56-DQ59 I/O1-I/O4 D13 I/O1-I/O4 D14 DQ28-DQ31 I/O1-I/O4 D7 A0-A11,(A12) VCC VSS D0-D15 C0-C15 DQ60-DQ63 I/O1-I/O4 D15 E2PROM (256wordx8bit) SA0 SA1 SA2 SCL SDA 4M x 64 DIMM Module Block Diagram Semiconductor Group 5 5 Page HYM 64(72)V1605/45GU-50/-60 16M x 64/72 DRAM Module AC Characteristics 5)6) TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns Parameter Symbol Limit Values -50 -60 min. max. min. max. common parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period for 2k-refresh Refresh period for 4k-refresh tRC 84 – 104 – tRP 30 – 40 – tRAS 50 10k 60 10k tCAS 8 10k 10 10k tASR 0 – 0 – tRAH 8 – 10 – tASC 0 – 0 – tCAH 8 – 10 – tRCD 12 37 14 45 tRAD 10 25 12 30 tRSH 13 15 – tCSH 40 50 – tCRP 5 – 5 – tT 1 50 1 50 tREF – 32 – 32 tREF – 64 – 64 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 16E Note 7 Read Cycle Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS tRAC tCAC tAA tOEA tRAL tRCS tRCH tRRH CAS to output in low-Z Output buffer turn-off delay tCLZ tOFF – 50 – 60 ns 8, 9 – 13 – 15 ns 8, 9 – 25 – 30 ns 8,10 – 13 – 15 ns 25 – 30 – ns 0 – 0 – ns 0 – 0 – ns 11 0 – 0 – ns 11 0 – 0 – ns 8 0 13 0 15 ns 12 Semiconductor Group 11 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
HYM72V1645GU-60	3.3V 16M x 64-Bit EDO-DRAM Module 3.3V 16M x 72-Bit EDO-DRAM Module	Siemens

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