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PDF HYM64V2005GU-60 Data sheet ( Hoja de datos )

Número de pieza HYM64V2005GU-60
Descripción 3.3V 2M x 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module
Fabricantes Siemens 
Logotipo Siemens Logotipo



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No Preview Available ! HYM64V2005GU-60 Hoja de datos, Descripción, Manual

3.3V 2M × 64-Bit EDO-DRAM Module
3.3V 2M x 72-Bit EDO-DRAM Module
168pin unbuffered DIMM Module
with serial presence detect
HYM64V2005GU-50/-60
HYM72V2005GU-50/-60
168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module
for PC main memory applications
1 bank 2M x 64, 2M x 72 organisation
Optimized for byte-write non-parity or ECC applications
Extended Data Out (EDO)
Performance:
tRAC
tCAC
tAA
tRC
tHPC
RAS Access Time
CAS Access Time
Access Time from Address
Cycle Time
EDO Mode Cycle Time
-50
50 ns
13 ns
25 ns
84 ns
20 ns
-60
60 ns
15 ns
30 ns
104 ns
25 ns
Single +3.3 V ± 0.3 V Power Supply
CAS-before-RAS refresh, RAS-only-refresh
Decoupling capacitors mounted on substrate
All inputs, outputs and clocks are fully LV-TTL compatible
Serial presence detects (optional)
Utilizes 2M × 8 -DRAMs in SOJ packages
2048 refresh cycles / 32 ms with 11 / 10 addressing (Row / Column)
Gold contact pad
Card Size: 133,35mm x 25,40 mm x 5,30 mm
This DRAM product module family is intended to be fully pin and architecture compatible
with the 168pin unbuffered SDRAM DIMM module family
Semiconductor Group
1
2.97

1 page




HYM64V2005GU-60 pdf
HYM 64(72)V2005GU-50/-60
2M x 64/72 DRAM Module
RAS0
WE0
OE0
CAS0
DQ0-DQ7
CAS1
DQ8-DQ15
CB0-CB7
CAS2
DQ16-DQ23
CAS3
DQ24-DQ31
I/O1-I/O8
D0
I/O1-I/O8
D1
I/O1-I/O8
D8
I/O1-I/O8
D2
I/O1-I/O8
D3
RAS2
WE2
OE2
CAS4
DQ32-DQ39
CAS5
DQ40-DQ47
CAS6
DQ48-DQ55
CAS7
DQ56-DQ63
I/O1-I/O8
D4
I/O1-I/O8
D5
I/O1-I/O8
D6
I/O1-I/O8
D7
A0-A10
VCC
VSS
D0-D8
C0-C8
E2PROM (256wordx8bit)
SA0
SA1
SA2
SCL
SDA
2M x 72 DIMM Module Block Diagram
Semiconductor Group
5

5 Page





HYM64V2005GU-60 arduino
HYM 64(72)V2005GU-50/-60
2M x 64/72 DRAM Module
AC Characteristics (contd’ ) 5)6)
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
-50 -60
min. max. min. max.
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) read-write
cycle time
tPRWC
58
68 –
CAS precharge to WE
tCPWD 41
49 –
Unit
ns
ns
16E
Note
CAS-before-RAS Refresh Cycle
CAS setup time
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
tCSR
tCHR
tRPC
tWRP
tWRH
10
10
5
10
10
10 –
10 –
5–
10 –
10 –
ns
ns
ns
ns
ns
Capacitance
TA = 0 to 70 °C; VCC = 3.3 V ± 0.3 V; f = 1 MHz
Parameter
Input Capacitance (A0 to A9)
Input Capacitance (RAS0, RAS2)
Input Capacitance (CAS0-CAS7)
Input Capacitance (WE0,WE2,OE0,OE2)
I/O Capacitance (DQ0-DQ63,CB0-CB8)
Input Capacitance (SCL, SA0-2)
Input/Output Capacitance (SDA)
Symbol
CI1
CI2
CI3
CI4
CIO1
Cs
Cs
Limit Values
min.
max.
– 55
– 50
– 10
– 50
– 11
–8
– 10
Unit
pF
pF
pF
pF
pF
pF
pF
Semiconductor Group
11

11 Page







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