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PDF HYB514171BJ-50 Data sheet ( Hoja de datos )

Número de pieza HYB514171BJ-50
Descripción 256k x 16-Bit Dynamic RAM
Fabricantes Siemens 
Logotipo Siemens Logotipo



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256k × 16-Bit Dynamic RAM
HYB 514171BJ-50/-60
Advanced Information
• 262 144 words by 16-bit organization
• 0 to 70 °C operating temperature
• Fast access and cycle time
• RAS access time:
50 ns (-50 version)
60 ns (-60 version)
• CAS access time:
15ns (-50, -60 version)
• Cycle time:
95 ns (-50 version)
110 ns (-60 version)
• Fast page mode cycle time
35 ns (-50 version)
40 ns (-60 version)
• Single + 5.0 V (± 10 %) supply with a
built-in VBB generator
• Low Power dissipation
max. 1045 mW active (-50 version)
max. 935 mW active (-60 version)
• Standby power dissipation
11 mW standby (TTL)
5.5 mW max. standby (CMOS)
• Output unlatched at cycle end allows
two-dimensional chip selection
• Read, write, read-modify write,
CAS-before-RAS refresh, RAS-only
refresh, hidden-refresh and fast page
mode capability
• 2 CAS / 1 WE control
• All inputs and outputs TTL-compatible
• 512 refresh cycles / 16 ms
• Plastic Packages:
P-SOJ-40-1 400 mil width
The HYB 514171BJ is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The
HYB 514171BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 514171BJ to be packed in a standard plastic 400 mil wide P-SOJ-40-1 package.
This package size provides high system bit densities and is compatible with commonly used
automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %)
power supply, direct interfacing with high performance logic device families such as Schottky TTL.
Semiconductor Group
1
1998-10-01

1 page




HYB514171BJ-50 pdf
HYB 514171BJ-50/-60
256k × 16 DRAM
Absolute Maximum Ratings
Operating temperature range ....................................................................................... 0 to + 70 °C
Storage temperature range.................................................................................... – 55 to + 150 °C
Input/output voltage ......................................................................................................... – 1 to 6 V
Power supply voltage........................................................................................................ – 1 to 6 V
Data out current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 5 ns
Parameter
Symbol
Limit Values Unit Notes
min.
max.
Input high voltage
VIH
Input low voltage
VIL
TTL Output high voltage (IOUT = – 5.0 mA)
VOH
TTL Output low voltage (IOUT = 4.2 mA)
VOL
Input leakage current, any input
II(L)
(0 V < VIN < VCC + 0.3 V, all other inputs = 0 V)
Output leakage current
(DO is disabled, 0 V < VOUT < VCC )
IO(L)
Average VCC supply current
-50 version ICC1
-60 version
2.4
– 1.0
2.4
– 10
– 10
VCC + 0.5 V
0.8 V
–V
0.4 V
10 µA
1
1
1
1
1
10 µA 1
190
mA 2, 3, 4
170
Standby VCC supply current
(RAS = LCAS = UCAS = WE = VIH)
Average VCC supply current during
RAS-only refresh cycles
-50 version
-60 version
ICC2
ICC3
2 mA
2, 4
190 mA
170
Average VCC supply current during
fast page mode operation
-50 version ICC4
-60 version
2, 3, 4
160 mA
150
Standby VCC supply current
(RAS = LCAS = UCAS = WE = VCC – 0.2 V)
Average VCC supply current during
CAS-before-RAS refresh mode
-50 version
-60 version
ICC5
ICC6
1 mA 1
2, 4
190 mA
170
Semiconductor Group
5
1998-10-01

5 Page





HYB514171BJ-50 arduino
HYB 514171BJ-50/-60
256k × 16 DRAM
VIH
RAS
VIL
UCAS
LCAS
VIH
VIL
Address
VIH
VIL
VIH
WE
VIL
VIH
OE
VIL
I/O
(Inputs)
VIH
VIL
I/O VOH
(Outputs) VOL
t RAS
t RC
t RCD
t CSH
t RSH
t CAS
t ASR
t RAD
t ASC
Row
t RAH
t WCS
t RAL
t CAH
Column
t CWL
t WP
t WCH
t RWL
t DS t DH
Valid Data IN
Hi Z
"H" or "L"
Write Cycle (Early Write)
t RP
t CRP
t ASR
Row
SPT03044
Semiconductor Group
11
1998-10-01

11 Page







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