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PDF HYB5118165BJ-50 Data sheet ( Hoja de datos )
| Número de pieza | HYB5118165BJ-50 | |
| Descripción | 1M x 16-Bit Dynamic RAM 1k & 4k Refresh | |
| Fabricantes | Siemens | |
| Logotipo |  |
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1M x 16-Bit Dynamic RAM
1k & 4k Refresh
(Hyper Page Mode- EDO)
HYB5116165BSJ -50/-60/-70
HYB5118165BSJ -50/-60/-70
Advanced Information
• 1 048 576 words by 16-bit organization
• 0 to 70 °C operating temperature
• Performance:
tRAC
tCAC
tAA
tRC
tHPC
RAS access time
CAS access time
Access time from address
Read/Write cycle time
Hyper page mode (EDO)
cycle time
-50 -60 -70
50 60 70 ns
13 15 20 ns
25 30 35 ns
84 104 124 ns
20 25 30 ns
• Single + 5 V (± 10 %) supply
• Low power dissipation
max. 1100 active mW ( HYB5118165BSJ-50)
max. 990 active mW ( HYB5118165BSJ-60)
max. 880 active mW ( HYB5118165BSJ-70)
max. 550 active mW ( HYB5116165BSJ-50)
max. 495 active mW ( HYB5116165BSJ-60)
max. 440 active mW ( HYB5116165BSJ-70)
11 mW standby (TTL)
5.5. mW standby (MOS)
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh
and Self Refresh
• Hyper page mode (EDO) capability
• All inputs, outputs and clocks fully TTL-compatible
• 1024 refresh cycles / 16 ms for HYB5118165BSJ (1k-Refresh)
• 4096 refresh cycles / 64 ms for HYB5116165BSJ (4k-Refresh)
• Plastic Package:
P-SOJ-42-1 400 mil
Semiconductor Group
1
1.96
1 page  
HYB 5116(8)165BSJ-50/-60/-70
1M x 16-EDO DRAM
I/O1 I/O2
I/O16
WE
.UCAS
.LCAS
&
No. 2 Clock
Generator
Data in
Buffer
16
Data out
Buffer
16
OE
Column
10 Address
A0 Buffer(10)
A1
A2
A3 Refresh
A4 Controller
A5
A6
A7 Refresh
A8 Counter (10)
A9
10
10 Column
Decoder
Sense Amplifier
I/O Gating
16
1024
x16
Row
10 Address
Buffers(10)
Row
Memory Array
10 Decoder 1024 1024x1024x16
RAS
No. 1 Clock
Generator
Voltage Down
Generator
VCC
VCC (internal)
Block Diagram for HYB 5118165BSJ
Semiconductor Group
5
5 Page 
HYB 5116(8)165BSJ-50/-60/-70
1M x 16-EDO DRAM
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during
a hyper page mode (EDO) cycle
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined
by the latter of tRAC, tCAC, tAA,tCPA, tOEA. tCAC is measured from tristate.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs
last.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain
open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.),
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh
Semiconductor Group
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet HYB5118165BJ-50.PDF ] | |
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