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PDF HYB5117805BSJ-50 Data sheet ( Hoja de datos )
| Número de pieza | HYB5117805BSJ-50 | |
| Descripción | 2M x 8-Bit Dynamic RAM 2k Refresh | |
| Fabricantes | Siemens | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HYB5117805BSJ-50 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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2M × 8-Bit Dynamic RAM
2k Refresh
(Hyper Page Mode-EDO)
HYB 5117805/BSJ-50/-60
HYB 3117805/BSJ-50/-60
Advanced Information
• 2 097 152 words by 8-bit organization
• 0 to 70 °C operating temperature
• Hyper Page Mode-EDO-operation
• Performance:
tRAC RAS access time
tCAC CAS access time
tAA Access time from address
tRC Read/Write cycle time
tHPC Hyper page mode (EDO) cycle time
-50 -60
50 60 ns
13 15 ns
25 30 ns
84 104 ns
20 25 ns
• Power dissipation:
Power Supply
Active
TTL Standby
CMOS Standby
HYB 5117805
-50 -60
5 ± 10%
440 385
11
5.5
HYB 3117805
-50 -60
3.3 ± 0.3 V
288 252
7.2
3.6
mW
mW
mW
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh
and test mode
• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
• 2048 refresh cycles / 32 ms (2k-refresh)
• Plastic Package: P-SOJ-28-3 400 mil
Semiconductor Group
1
1998-10-01
1 page  
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter
Symbol Limit Values
min.
max.
Average VCC supply current
ICC1
-50 ns version
-60 ns version
(RAS, CAS, address cycling: tRC = tRC MIN.)
Standby VCC supply current (RAS = CAS = VIH) ICC2
Average VCC supply current, during RAS-only ICC3
refresh cycles
-50 ns version
-60 ns version
(RAS cycling, CAS = VIH, tRC = tRC MIN.)
Average VCC supply current, during hyper page ICC4
mode (EDO)
-50 ns version
-60 ns version
(RAS = VIL, CAS, address cycling: tPC = tPC MIN.)
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
Average VCC supply current, during CAS-
ICC6
before-RAS refresh mode
-50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC MIN.)
–
–
–
–
–
–
–
–
–
–
80
70
2
80
70
35
30
1
80
70
Unit Test
Condition
mA 2, 3, )4
mA 2, 3, 4
mA –
mA 2, 4
mA 2, 4
mA 2, 3, 4
mA 2, 3, 4
mA 1
mA 2, 4
mA 2, 4
Capacitance
TA = 0 to 70 °C, VCC = 5 V ± 10 %, f = 1 MHz
Parameter
Input capacitance (A0 to A10)
Input capacitance (RAS, CAS, WE, OE)
I/O capacitance (I/O1 - I/O8)
Symbol
CI1
CI2
CIO
Limit Values
min.
max.
–5
–7
–7
Unit
pF
pF
pF
Semiconductor Group
5
1998-10-01
5 Page 
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
VIH
RAS
VIL
VIH
CAS
VIL
Address
VIH
VIL
VIH
WE
VIL
VIH
OE
VIL
I/O
(Inputs)
VIH
VIL
I/O VOH
(Outputs) VOL
t RAS
t RC
t RCD
t CSH
t RSH
t CAS
t ASR
t RAD
t ASC
Row
t RAH
t WCS
t RAL
t CAH
Column
t CWL
t WP
t WCH
t RWL
t DS t DH
Valid Data IN
Hi Z
"H" or "L"
Write Cycle (Early Write)
t RP
t CRP
t ASR
Row
SPT03026
Semiconductor Group
11
1998-10-01
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet HYB5117805BSJ-50.PDF ] | |
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