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PDF TDA7310 Data sheet ( Hoja de datos )
| Número de pieza | TDA7310 | |
| Descripción | SERIAL BUS CONTROLLED AUDIO PROCESSOR | |
| Fabricantes | ST Microelectronics | |
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® TDA7310
SERIAL BUS CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER:
- 4 STEREO INPUTS
- ONE DIFFERENTIAL STEREO INPUT FOR
REMOTE SOURCES
SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTION TO DIFFERENT SOURCES
INPUT AND OUTPUT FOR EXTERNAL
EQUALIZER OR NOISE REDUCTION SYS-
TEM
VOLUME CONTROL IN 1.25dB STEPS
LOUDNESS FUNCTION
TREBLE AND BASS CONTROL
FOUR SPEAKER ATTENUATORS:
- 4 INDEPENDENT SPEAKERS CONTROL
IN 1.25dB STEPS FOR BALANCE AND
FADER FACILITIES
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL BUS
SELECTABLE CHIP ADDRESS DEDICATED
PIN
PQFP44 (10 x 10)
ORDERING NUMBER: TDA7310
DESCRIPTION
The TDA7310 is a volume, tone (bass and treble)
and fader (front/rear) processor for high quality audio
applications in car radio and Hi-Fi systems.
Loudness and selectable input gain are provided.
The control of all fuctions is accomplished by serial
bus microprocessor interface.
The AC signal setting is obtained by resistor networks
andswitches combined with operationalamplifiers.
Thanks to the used BIPOLAR/CMOS Tecnology,
Low Distortion, Low Noise and DC stepping are ob-
tained.
PIN CONNECTION (Top view)
November 1999
1/15
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1 page  
TDA7310
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
TREBLE CONTROL (1)
Test Condition
Min. Typ. Max. Unit
Control Range
Step Resolution
VDC DC Steps
AUDIO OUTPUTS
adjacent control steps
+14 dB
2 dB
0.1 mV
GENERAL
Clipping Level
Output Load Resistance
Output Load Capacitance
Output resistance
DC Voltage Level
d = 0.3%
2.5 Vrms
2 KΩ
10 nF
75 120 Ω
4.2 4.5 4.8
V
eNO Output Noise
S/N Signal to Noise Ratio
d Distortion
Sc Channel Separation left/right
Total Tracking error
BUS INPUTS
BW = 20-20KHz, flat
output muted
all gains = 0dB
all gains = 0dB; VO = 1Vrms
VIN = 1Vrms
AV = 0 to -20dB
-20 to -60 dB
2.5
5 15
106
0.01
80 103
01
02
µV
µV
dB
%
dB
dB
dB
VIL Input Low Voltage
VIH Input High Voltage
VO Output Voltage SDA
Acknowledge
LOUDNESS SWITCH
IO = 1.6mA
1V
3V
0.4 V
VIL Input Low Voltage
VIH Input High Voltage
IIN Input Current
DC Step
ON ← → OFF position
1V
3V
-5 +5 µA
0.1 mV
Loudness OFF = pin38 Open; Loudness ON = pin 38 Closed to GND
ADDRESS PIN (Internal 50KΩ pull down resistor)
VIL Input Low Voltage
VIH Input High Voltage
IIN Input Current
VCC -1V
1V
V
µA
Notes:
(1) Bass and Treble response see attached diagram (fig.17). The center frequency and quality of the resonance behaviour can be choosen by
the external circuitry. A standard first order bass response can be realized by a standard feedback network
(2) The selected input is grounded thru the 2.2µF capacitor.
5/15
5 Page 
TDA7310
APPLICATION INFORMATION (continued)
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the µP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7310
address (the 8th bit of the byte must be 0). The
TDA7310 must always acknowledge at the end
of each transmitted byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
TDA7310 ADDRESS
MSB first byte
LSB MSB
S 1 0 0 0 1 0 A 0 ACK
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s
DATA
LSB MSB
ACK
DATA
Data Transferred (N-bytes + Acknowledge)
LSB
ACK P
SOFTWARE SPECIFICATION
Chip address
10001
MSB
A = LOGIC LEVEL ON PIN ADDR
0
A0
LSB
DATA BYTES
MSB
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
B2 B1 B0 A2 A1
0 B1 B0 A2 A1
1 B1 B0 A2 A1
0 B1 B0 A2 A1
1 B1 B0 A2 A1
0 G1 G0 S2 S1
1 0 C3 C2 C1
1 1 C3 C2 C1
Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 6.25dB steps
STATUS AFTER POWER ON RESET
Volume
speaker
audio Switch
bass
treble
gain
-77.5dB
-37.5dB
Stereo 5
+2dB
+2dB
0dB
LSB FUNCTION
A0 Volume control
A0 Speaker ATT LR
A0 Speaker ATT RR
A0 Speaker ATT LF
A0 Speaker ATT RF
S0 Audio switch
C0 Bass control
C0 Treble control
11/15
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| PDF Descargar | [ Datasheet TDA7310.PDF ] | |
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