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PDF TDA6651TT Data sheet ( Hoja de datos )
| Número de pieza | TDA6651TT | |
| Descripción | 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA6650TT; TDA6651TT
5 V mixer/oscillator and low noise
PLL synthesizer for hybrid
terrestrial tuner (digital and analog)
Product specification
Supersedes data of 2003 Sep 11
2004 Mar 22
1 page  
Philips Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
Product specification
TDA6650TT;
TDA6651TT
5 BLOCK DIAGRAM
handbook, full pagewidth
n.c. VCCA
21 (18)
26 (13)
TDA6650TT
(TDA6651TT)
4 (35)
LBIN
LOW
INPUT
BS1
IFFIL1
IFFIL2
IFOUTA
IFOUTB
6 (33)
7 (32) 28 (11) 27 (12)
IF
AMP
(30) 9
AGC
DETECTOR
AGC
flag
AL0, AL1, AL2 ATC
(10) 29
LOW
MIXER
(1) 38
BS1
LOW
OSCILLATOR (2) 37
AGC
IFGND
LOSCIN
LOSCOUT
3 (36)
MBIN
MID
INPUT
BS2
MID
MIXER
(5) 34
BS2
MID
OSCILLATOR (4) 35
MOSCIN1
MOSCIN2
HBIN1
HBIN2
1 (38)
2 (37)
HIGH
INPUT
BS1 . BS2
HIGH
MIXER
5 (34)
RFGND
BS1 . BS2
HIGH
OSCILLATOR
(9) 30
(8) 31
(7) 32
(6) 33
(3) 36
VCCD 24 (15)
R0, R1,
N [14:0]
R2
OUTPUT
BUFFER
(21) 18
FRACTIONAL
DIVIDER
XTAL1
XTAL2
19 (20)
20 (19)
CRYSTAL
OSCILLATOR
FRACTIONAL
CALCULATOR
REFERENCE
DIVIDER
PHASE
COMPARATOR
CHARGE
PUMP
T0, T1, T2
LOOP
AMP
(17) 22
(16) 23
SCL
SDA
AS
BVS
15 (24)
16 (23)
17 (22)
13 (26)
I2C-BUS
TRANSCEIVER
AGC
LOCK
T0, T1, CP0, CP1,
DETECTOR
T2
CP2
BAND SWITCH
OUTPUT PORTS
FRACTIONAL
BS5- SPURIOUS
BS1 COMPENSATION
POR
ADC
14 8 10 11 12
(25) (31) (29) (28) (27)
ADC/
BS3
BS1
BS5
BS4
BS2
(14) 25
FCE723
The pin numbers in parenthesis represent the TDA6651TT.
HOSCIN1
HOSCOUT1
HOSCOUT2
HOSCIN2
OSCGND
XTOUT
VT
CP
PLLGND
Fig.1 Block diagram.
2004 Mar 22
5
5 Page 
Philips Semiconductors
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
Product specification
TDA6650TT;
TDA6651TT
8.1.2 XTOUT OUTPUT BUFFER AND MODE SETTING
The crystal frequency can be sent to pin XTOUT and used
in the application, for example to drive the clock input of a
digital demodulator, saving a quartz crystal in the bill of
material. To output fxtal, it is necessary to set T[2:0] to 001.
If the output signal on this pin is not used, it is
recommended to disable it, by setting T[2:0] to 000. This
pin is also used to output 1/2fdiv and fcomp in a test mode.
At Power-on, the XTOUT output buffer is set to on,
supplying the fxtal signal. The relation between the signal
on pin XTOUT and the setting of theT[2:0] bits is given in
Table 6.
Table 6 XTOUT buffer status and test modes
T2 T1 T0 PIN XTOUT
MODE
0 0 0 disabled
normal mode with XTOUT buffer off
0
0
1 fxtal (4 MHz)
normal mode with XTOUT buffer on
0 1 0 1/2fdiv
charge pump off
0
1
1 fxtal (4 MHz)
switch ALBC on or off (note 1)
1 0 0 fcomp
test mode
1 0 1 1/2fdiv
test mode
1
1
0 fxtal (4 MHz)
charge pump sinking current (note 2)
1 1 1 disabled
charge pump sourcing current
Notes
1. Automatic Loop Bandwidth Control (ALBC) is disabled at Power-on reset. After Power-on reset this feature is
enabled by setting T[2:0] = 011. To disable again the ALBC, set T[2:0] = 011 again. This test mode acts like a toggle
switch, which means each time it is set the status of the ALBC changes. To toggle the ALBC, two consecutive Control
byte 1s (CB1), should be sent: one byte with T[2:0] = 011 indicating that ALBC will be switched on or off and one byte
programming the test mode to be selected (see Table 23, example of I2C-bus sequence).
2. This is the default mode at Power-on reset. This mode disables the tuning voltage.
8.1.3 STEP FREQUENCY SETTING
The step frequency is set by three bits, giving five steps to cope with different application requirements.
The reference divider ratio is automatically set depending on bits R2, R1 and R0. The phase detector works at either
4, 2 or 1 MHz.
Table 7 shows the step frequencies and corresponding reference divider ratios. When the value of bits R2, R1 and R0
are changed, it is necessary to re-send the data bytes DB1 and DB2.
Table 7 Reference divider ratio select bits
R2 R1 R0
000
001
010
011
100
101
110
111
REFERENCE
DIVIDER RATIO
2
1
1
4
1
−
−
−
FREQUENCY
COMPARISON
2 MHz
4 MHz
4 MHz
1 MHz
4 MHz
−
−
−
FREQUENCY STEP
62.5 kHz
142.86 kHz
166.67 kHz
50 kHz
125 kHz
reserved
reserved
reserved
2004 Mar 22
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA6651TT.PDF ] | |
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