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PDF TDA5931 Data sheet ( Hoja de datos )
| Número de pieza | TDA5931 | |
| Descripción | Video IF Amplifier and Demodulator with Full-SCART | |
| Fabricantes | Siemens Semiconductor | |
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Video IF Amplifier and Demodulator
with Full-SCART
Features
q Multistandard video IF
q Interference suppression circuitry
q Mean/peak value control
q Area of application: TV set with Full-SCART
TDA 5931-65
Bipolar IC
P-DIP-18
Type
TDA 5931-65
Ordering Code
Q67000-A5136
Package
P-DIP-18
Functional Description
Video IF for all European standards for positive and negative modulation. The video section
contains a Full-SCART interface. An output for the demodulated video signal (pin 9) allows the
insertion of a sound trap into the signal path to the input or the SCART switch and the SCART output
buffer amplifier (pin 7). The analog setting function (delayed AGC threshold) is controlled via a
potentiometer, all other switch functions are controlled via open-collector transistors.
Circuit Description
The component includes a four-stage, capacitively coupled, symmetrically designed and controlled
amplifier, a limiter with selection, and a mixer for quasi-synchronous demodulation of positive and
negative modulated IF signals. In addition a video output amplifier and noise suppression circuitry
are included. This output is used for generating the AGC voltage. The AGC for both modulation
types has been realized as integral AGC with noise free peak and mean value detector (only for
positive modulation). For SCART applications this output is switched a video source switch with two
inputs (for the demodulator signal or SCART socket) and two outputs (SCART- and TV output). The
demodulator output (pin 9) provides a video signal output level 3 dB higher than the level required
for the operation of the TV set or to drive the SCART connector. Therefore it is possible to insert a
sound trap in between this output and the input of the SCART switch (pin 7). The insertion loss of
the sound trap has to attenuate the signal level at pin 9 by a factor 2/3 or 3 dB (AC and DC) to avoid
distortions in the SCART switch.
The delayed tuner AGC is generated by a threshold amplifier driven by the control voltage. The
amplifier response can be controlled by means of an external potentiometer. (The increase of the
tuner AGC voltage shall create a higher tuner gain = positive control).
Semiconductor Group
31
06.94
1 page  
TDA 5931-65
Characteristics
TA = 25 ˚C; VS = 12 V
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Static Characteristics
Total current consumption
– I5
38.5 56
71.5 mA V1/16 = 10 mVrms
AGC Voltage
Min. AGC
Max. AGC
V16 0 0.1 0.5 V V1/16 = 45 µVrms
V16 2.6 2.85 6.0 V V1/16 = 175 mVrms
AGC-Time Constant (by neg. modulation)
Charge current (Imax:2)
Discharge current
Charge/discharge ratio
I16
– I16
V16
0.55
13
55
0.7
17
82
0.95
23
140
mA V16 = 2 V; V6 < 2.2 V
µA V16 = 2 V; V6 > 2.8 V
AGC-Time Constant (by pos. modulation)
Charge current
Discharge current
Discharge current
Charge/discharge ratio
I16
– I16
– I16
V16
1.1 1.4 1.7 mA V16 = 2 V; V6 ≥ 4.1 V
0.15 0.25 0.35 µA V16 = 2 V;
3.1 V < V6 < 4.1 V
70 90 110 µA V16 = 2 V; V6 < 2.3 V
4000 5600 9000
Averaging by Pos. Modulation
White level
Zero carrier level
Tuner AGC threshold
I5 = Imax:2
V13
V13
V14
I14
V16
V16
4.9
3.3
4.2
650
2.8
0.33
5.7
3.7
4.5
850
3.1
0.38
6.5
4.1
4.8
1050
3.4
0.43
V
V
V
µA
V
V
V1/18 = 10 mVrms
V1/18 = 0 V; V16 = 3 V
R14/17 = ∞
V14 = 0 V
R14/17 = 10 kΩ
R14/17 = 10 Ω
The characteristics data apply to the supply voltage range VS stated or in case of alignment to the
alignment instructions (see page 40). All static voltages are referenced to ground if not stated
otherwise.
The input levels are given as rms values referenced to synchronous peak fPC = 38.9 MHz.
Semiconductor Group
35
5 Page 
TDA 5931-65
Alignment Instructions
At a video carrier input level of V1/18 = 4 mVrms, fPC = 38.9 MHz and a superimposed AGC voltage
of V16 = 1.5 V the tank circuit is aligned that way, that at the positive video output the demodulated
video signal 6 Vpp is at its maximum.
As a modulation every sufficient video test pattern can be used. Then the superimposed AGC-
control voltage at pin 16 is reduced until the video signal has an amplitude of approx. 2 Vpp. The
video signal is then fine tuned for its maximum.
The adjustment is not critical due to the wide maximum.
The adjustment can also be performed regarding intercarrier signal to noise ratio, differential gain or
2T-pulse response.
Semiconductor Group
41
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet TDA5931.PDF ] | |
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