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PDF TDA1592T Data sheet ( Hoja de datos )
| Número de pieza | TDA1592T | |
| Descripción | PLL stereo decoder and noise blanker | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA1592
PLL stereo decoder and noise
blanker
Preliminary specification
Supersedes data of June 1993
File under Integrated Circuits, IC01
1996 May 31
1 page  
Philips Semiconductors
PLL stereo decoder and noise blanker
Preliminary specification
TDA1592
FUNCTIONAL DESCRIPTION
The MPX input of the TDA1592 (pin 20) is the null-node of
an operational amplifier with internal feedback resistor.
Adapting the stereo decoder input to the level of the FM
demodulator output is realized by the value of input
resistor Rin (see Fig.3). The total gain of the stereo
decoder is applicable by varying the feedback resistors
Rout (pins 9, 10, 11 and 12) of the output operational
amplifiers (see Fig.4).
The input amplifier is followed by an integrated 4th order
Bessel low-pass filter with a cut-off frequency of 80 kHz.
It provides necessary signal delay for noise blanking and
damping of high frequency interferences at the stereo
decoder input.
The soft mute facility (pin 8) provides silent tuning for RDS
processing. The mute time constant may be adjusted from
pin 8. In mute position and the VCO switched off (pin 7),
the output amplifiers can be used for cassette playback,
AM stereo purpose or other signal sources.
The voltage to current converted MPX signal is fed to
phase detector, pilot detector and pilot canceller circuits.
The oscillator is alignment-free with an external ceramic
resonator at 456 kHz as reference (pin 2). The required
19 kHz and 38 kHz signals are generated by division of the
oscillator output signal in a logical circuit. For regeneration
of the 38 kHz subcarrier, a PLL is used. The 19 kHz
quadrature phase signal is fed to the 19 kHz
phase detector, where it is compared with the incoming
pilot tone. The DC output signal of the phase detector
(pin 1) controls the oscillator (PLL).
The pilot presence detector is driven by internally
generated in-phase 19 kHz. Its pilot-dependent DC output
voltage (pin 19) is fed to a threshold switch, which
activates the pilot indicator logic output (pin 18) and turns
the stereo decoder to stereo operation. The same
DC voltage is used to control the amplitude of an
anti-phase internally generated 19 kHz signal. In the
pilot canceller, the pilot tone is compensated by this
anti-phase 19 kHz signal.
The pilot cancelled signal is fed to the multiplex decoder.
There, the side signal is demodulated and combined with
the main signal in a matrix to left and right audio channel.
Compensation for roll-off in the incoming MPX signal
caused by IF filters and FM demodulator is realized by
corresponding side signal amplification.
A smooth mono to stereo take-over, which is controlled by
the level detector voltage of the IF part, is achieved by the
SNC (pins 16 and 17; see Fig.6).
From the output of the MPX demodulator the signals are
fed to 2-pole low-pass filters with a cut-off frequency of
30 kHz to provide additional signal delay for noise blanking
and attenuation of the subcarrier and its harmonics.
These filters are followed by the noise suppression gates,
which are combined with de-emphasis and HCC. The
de-emphasis is defined by internal resistors (aligned by an
external current) and external capacitors (pins 13 and 14).
For HCC, the de-emphasis time constant can be changed
to higher values (pins 15 and 17; see Figs 7 to 9). This
function is controlled by an analog input signal, derived
from the level detector voltage of the IF part. When the
VCO is turned off (pin 7 to GND), de-emphasis is reduced
to 20 µs for full frequency response when AM-AF is fed
through the stereo decoder. De-emphasis remains
controllable.
From the gate circuits audio is fed through internal series
resistors to the inverting inputs of the output operational
amplifiers (pins 9 and 12), which can also be used as
signal inputs for cassette playback or other sources when
the mute is activated. The gain of these amplifiers is
defined by external feedback resistors Rout
(pins 9, 10, 11 and 12).
The input of the ignition noise blanker is the null node of an
operational amplifier (pin 6). It can be driven by the level
detector output of the FM-IF limiter and/or the MPX signal.
Its sensitivity is dependent on the value of the series input
resistor at pin 6.
The operational amplifier output signal is fed through an
integrated 120 kHz high-pass filter, becomes amplified
and is then fed in parallel to the noise detector and the
interference detector. The noise detector is a negative
peak detector. Its output (pin 8) controls the trigger
sensitivity (prevention to false triggering at noisy input
signals) and the attenuation of the input operational
amplifier. The output of the interference detector, when
receiving a steep pulse, triggers a mono flip-flop, which is
a part of the pulse former circuit. The time constant of the
mono flip-flop is defined by an external capacitor (pin 7)
and its output activates the blanking gates in the audio.
1996 May 31
5
5 Page 
Philips Semiconductors
PLL stereo decoder and noise blanker
Preliminary specification
TDA1592
handbook, full pagewidth
2
Vo
(dB)
0
−2
−4
−6
−8
−10
−12
10
(1) V15-17 = 0.
(2) V15-17 = −300 mV.
(1)
(2)
MED732
10 2
103
10 4
AFout (Hz)
10 5
Fig.8 HCC with pre-emphasis as a function of audio frequency.
2
handbook, full pagewidth
Vo 0
(dB)
−2
MED733
(1)
−4
−6
−8 (2)
−10
−12
−14
−16
−18
10
10 2
10 3
10 4
AFout (Hz)
10 5
(1) V15-17 = 0.
(2) V15-17 = −300 mV.
Fig.9 HCC as a function of audio frequency (pin 7 connected to GND; without pre-emphasis).
1996 May 31
11
11 Page | ||
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| PDF Descargar | [ Datasheet TDA1592T.PDF ] | |
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