PDF TDA1548T Data sheet ( Hoja de datos )

Número de pieza	TDA1548T
Descripción	Bitstream continuous calibration filter-DAC with headphone driver and DSP
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET TDA1548T Bitstream continuous calibration filter-DAC with headphone driver and DSP Product speciﬁcation Supersedes data of 1995 Aug 02 File under Integrated Circuits, IC01 1995 Nov 15 1 page Philips Semiconductors Bitstream continuous calibration ﬁlter-DAC with headphone driver and DSP Product speciﬁcation TDA1548T PINNING SYMBOL PIN DESCRIPTION VSSO VCOM VOL 1 operational ampliﬁer ground 2 common output pin 3 left channel audio voltage output FILTCL 4 capacitor for left channel ﬁrst-order ﬁlter function should be connected between this pin and VOL (pin 3) MODE0 5 mode 0 selection pin MODE1 6 mode 1 selection pin BCK 7 bit clock input WS 8 word select input DATA 9 data input VDDD VSSD SYSCLK IF1 10 digital supply voltage 11 digital ground 12 system clock 64fs, 256fs or 384fs 13 input format selection 1 IF2 14 input format selection 2 DEEM 15 de-emphasis input (fs = 44.1 kHz) (active HIGH) MUTE 16 soft-mute input (active HIGH) CLSEL 17 system clock selection input ADref 18 reference voltage output to external potentiometer ADTR 19 analog sense input for treble setting ADBB 20 analog sense input for bass boost setting ADVC 21 analog sense input for volume control setting AD3S 22 3-position switch input for ﬂat/min/max setting VDDA VSSA Vref FILTCR 23 analog supply voltage 24 analog ground 25 internal reference voltage (0.5VDDA typ) 26 capacitor for right channel ﬁrst-order ﬁlter function should be connected between this pin and VOR (pin 27) VOR 27 right channel audio voltage output VDDO 28 operational ampliﬁer supply voltage handbook, halfpage VSSO 1 VCOM 2 VOL 3 28 VDDO 27 VOR 26 FILTCR FILTCL 4 MODE0 5 MODE1 6 BCK 7 WS 8 25 Vref 24 VSSA 23 VDDA 22 AD3S TDA1548T 21 ADVC DATA 9 20 ADBB VDDD 10 VSSD 11 SYSCLK 12 19 ADTR 18 ADref 17 CLSEL IF1 13 16 MUTE IF2 14 15 DEEM MGC669 Fig.2 Pin configuration. 1995 Nov 15 5 5 Page Philips Semiconductors Bitstream continuous calibration ﬁlter-DAC with headphone driver and DSP Product speciﬁcation TDA1548T DC CHARACTERISTICS All voltages referenced to ground (pins 1, 11 and 24); VDDD = VDDA = VDDO = 3 V; Tamb = 25 °C, RL = 32 Ω (note 1); common operational ampliﬁer application; unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS VDDD VDDA VDDO IDDD IDDA IDDO Ptot digital supply voltage pin 10 note 2 analog supply voltage pin 23 note 2 opamp supply voltage pin 28 note 2 digital supply current at digital silence analog supply current at digital silence opamp supply current at digital silence; note 3 total power dissipation note 3 Digital inputs VIH HIGH level input voltage on pins 5 to 9 and 12 to 17 VIL LOW level input voltage on pins 5 to 9 and 12 to 17 \|ILI\| input leakage current on pins 7 to 9 and 12 to 17 CI input capacitance on pins 5 to 9 and 12 to 17 MIN. 2.7 2.7 2.7 − − − − TYP. 3.0 3.0 3.0 4.5 4.5 6.0 50 MAX. 4.0 4.0 4.0 − − − − UNIT V V V mA mA mA mW 0.7VDDD − −− −− −− −V 0.3VDDD V 10 µA 10 pF Analog inputs pins ADVC, ADBB, ADTR and AD3S RES input resolution − CI input capacitance RI input resistance pins ADBB, ADTR and ADVC pin AD3S − 1 − −6 10 − −− 20 − bit pF MΩ kΩ Analog reference pin ADref VADref RL(ADref) reference voltage pin 18 reference output load pin 18 Analog audio pins Vref RO RCONV reference voltage pin 25 output resistance pin 25 current-to-voltage conversion resistor with respect to VSSO IO(max) CL maximum output current output load capacitance (THD + N)/S < 0.1% note 4 0.45VDDA 0.5VDDA 0.55VDDA V 3.0 − − kΩ 0.45VDDA − − 0.5VDDA 3 1.2 0.55VDDA − − V kΩ kΩ − 35 − mA − − 50 pF Notes 1. RL is the AC impedance of the external circuitry connected to the audio outputs of the application circuit. 2. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 3. No operational amplifier load resistor. 4. Load capacitance greater than 50 pF, an inductor of 22 µH connected in parallel with a resistor of 270 Ω must be inserted between the load and the operational amplifier output. 1995 Nov 15 11 11 Page

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