PDF TDA1305T Data sheet ( Hoja de datos )

Número de pieza	TDA1305T
Descripción	Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC BCC-DAC2
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET TDA1305T Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2) Preliminary speciﬁcation Supersedes data of September 1994 File under Integrated Circuits, IC01 1995 Dec 08 1 page Philips Semiconductors Stereo 1fs data input up-sampling ﬁlter with bitstream continuous dual DAC (BCC-DAC2) PINNING SYMBOL VDDA VSSA TEST1 BCK WS DATA CLKS1 CLKS2 VSSD VDDD TEST2 SYSCLKI n.c. n.c. VSSD SYSCLKO DEEM1 DEEM2 MUSB DSMB ATSB VOL FILTCL FILTCR VOR Vref VSSO VDDO PIN DESCRIPTION 1 analog supply voltage 2 analog ground 3 test input; pin should be connected to ground (internal pull-down resistor) 4 bit clock input 5 word select input 6 data input 7 clock selection 1 input 8 clock selection 2 input 9 digital ground 10 digital supply voltage 11 test input; pin should be connected to ground (internal pull-down resistor) 12 system clock input 13 not connected (this pin should be left open-circuit) 14 not connected (this pin should be left open-circuit) 15 digital ground 16 system clock output 17 de-emphasis on/off; fDEEM 32 kHz, 44 kHz and 48 kHz 18 de-emphasis on/off; fDEEM 32 kHz, 44 kHz and 48 kHz 19 mute input (active LOW) 20 double-speed mode input (active LOW) 21 12 dB attenuation input (active LOW) 22 left channel output 23 capacitor for left channel 1st order ﬁlter function should be connected between pins 22 and 23 24 capacitor for right channel 1st order ﬁlter function should be connected between pins 25 and 24 25 right channel output 26 internal reference voltage for output channels (0.5VDD) 27 operational ampliﬁer ground 28 operational ampliﬁer supply voltage 1995 Dec 08 5 Preliminary speciﬁcation TDA1305T Fig.2 Pin configuration. 5 Page Philips Semiconductors Stereo 1fs data input up-sampling ﬁlter with bitstream continuous dual DAC (BCC-DAC2) Preliminary speciﬁcation TDA1305T SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Serial input data timing (see Fig.4) fBCK bit-clock input (data input fsys = 384fs rate) frequency fsys = 256fs fWS word select input frequency normal speed double speed − 48fs − MHz − 64fs − MHz 25 44.1 48 kHz 50 88.2 96 kHz tr tf tH tL tsu th tsuWS thWS rise time fall time bit clock time HIGH bit clock time LOW data set-up time data hold time word select set-up time word select hold time −− −− 55 − 55 − 40 − 10 − 40 − 10 − 20 ns 20 ns − ns − ns − ns − ns − ns − ns Notes 1. All VDD and VSS pins must be connected externally to the same supply. 2. Vripple = 1% of supply voltage; fripple = 100 Hz. Ripple rejection RR to VDDA is dependent on the value of the external capacitor (CEXT3 in Fig.1) connected to Vref. The value here assumes that CEXT3 = 1 µF. 3. Minimum VIL and maximum VIH are peak values to allow for transients. 4. ILImni measured at VI = 0 V; ILImax measured at VI = 5.5 V. 5. Reference levels = 10% and 90%. ANALOG CHARACTERISTICS VDD = VDDA = VDDO = 5 V; VSS = 0 V; Tamb = 25 °C; unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS MIN. Reference values Vref RCONV reference voltage level current-to-voltage conversion resistor 2.45 1.6 Analog outputs RES resolution VFS(rms) full-scale output voltage (pins 23 and 25) (RMS value) VOFF TCFS output voltage DC offset with respect to reference voltage level Vref full scale temperature coefﬁcient − 1.425 −80 − TYP. MAX. 2.5 2.55 2.2 2.8 − 18 1.5 1.575 −65 −50 ±100 × 10−6 − UNIT V kΩ bit V mV 1995 Dec 08 11 11 Page

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