PDF TD62824P Data sheet ( Hoja de datos )

Número de pieza	TD62824P
Descripción	8x3 PARALLEL SHIFT REGISTER/DRIVER
Fabricantes	Toshiba
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No Preview Available ! TD62824P TOSHIBA BIPOLAR DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TD62824P 8 × 3 PARALLEL SHIFT REGISTER / DRIVER The TD62824P is a general purpose 24 bit driver IC consisting of 8 block 3 bit shift register and 24 bit driver (open collector). The TD62824P is best suited as a 24 dot printer head driver. FEATURES l Power−down function for reducing power consumption during standby or when printing is not made. (ICC off < 10 µA) l Independent 2 output enable terminals (even / add outputs) l Effective as measures for regenerative effect during high−speed and high−density printing. l 8bit parallel input and 3bit parallel shift configuration : High−speed operation and direct interface with CPU. l Large output drive capacity l Output with standing voltage ········ 30 V Output current ································ 80 mA DC 150 mA 10% l Built−in CR−Timer for load burning prevention. l Less output saturation voltage difference in package : Within ±50mV (standard) at IOUT = 120 mA Weight: 6.37 g (Typ.) PIN CONNECTION (TOP VIEW) 1 2001-07-05 1 page TD62824P ELECTRICAL CHARACTERISTICS (Ta = 25°C) CHARACTERISTIC Input Voltage “H” Level “L” Level Input Current Output Leak Current “H” Level “L” Level Output Saturation Supply Current Input Voltage Hysteresis Voltage “H” Level “L” Level SYMBOL VIH VIL TEST CIR− CUIT ― ― TEST CONDITION ― ― MIN TYP. MAX UNIT 2.0 ― VCC V 0 ― 0.6 IIH ― VCC = 5.5 V, VIN = 2.4 V VCC = 5.5 V, VIN = 5.5 V ― 0.12 0.2 mA ― 0.32 0.5 IIL ― VCC = 5.5 V, VIN = 0.3 V ― ― 30 µA IOH ― VCC = 4.5 V, VOUT = 28 V ― ― 30 µA VOL ICC ICC (ON) ICC (OFF) ― VCC = 4.5 V, IOUT = 60 mA VCC = 4.5 V, IOUT = 120 mA PD = GND ― VCC = 5.5 V PD = GND ALL OUTPUT “ON” PD = GND ALL OUTPUT “OFF” ― ― ― ― ― 0.9 1.15 1.1 1.5 V ― 10 µA 12 20 mA 9.5 16 VTH+ ― ― 2.5 2.8 3.1 V VTH− ― 1.2 1.4 1.6 VH ― ― ― 1.4 ― V SWITCHING CHARACTERISTICS (Ta = 25°C, VCC = 5.0 V) CHARACTERISTIC Max. Operating Frequency CK−OUT SYMBOL fMAX TEST CIR− CUIT TEST CONDITION Propagation “H” Level E−OUT OSC−OUT tpLH Delay Time “L” Level Min. Pulse Width PD−OUT CK−OUT E−OUT OSC−OU T CLOCK CLOCK ENABLE tpHL tw MIN ― RL = 68 Ω, CL = 15 pF VIH = 3.0 V, VIL = 0 V ENABLE Set Up Time Data Hold Time CK−DATA PD Max. Clock Rise Time Max. Clock Fall Time Enable Output Pulse Width tsetup thold tr tf tw ON ― REXT = 10 kΩ, CEXT = 10 µF MIN TYP. MAX UNIT 500 850 ― ― 0.7 1.3 ― 5.5 10 ― 7.5 13 ― 9 30 ― 0.8 1.3 ― 0.6 1.3 ― 0.8 1.3 ― 0.06 0.1 ― 1.1 1.85 ― 0.1 0.2 ― 1.0 2.0 ― −0.2 0 ― −0.22 0.8 ― 0.15 0.5 ―― 5 ―― 5 ―3― kHz µs µs µs µs µs ms ms 5 2001-07-05 5 Page

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