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PDF TC7650CPA Data sheet ( Hoja de datos )
| Número de pieza | TC7650CPA | |
| Descripción | Chopper Stabilized Operational Amplifier | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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TC7650
Chopper Stabilized Operational Amplifier
Features
• Low Input Offset Voltage: 0.7µV Typ
• Low Input Offset Voltage Drift: 0.05µV/°C Max
• Low Input Bias Current: 10pA Max
• High Impedance Differential CMOS Inputs: 1012Ω
• High Open Loop Voltage Gain: 120dB Min.
• Low Input Noise Voltage: 2.0µVp-p
• High Slew Rate: 2.5V/µsec.
• Low Power Operation: 20mW
• Output Clamp Speeds Recovery Time
• Compensated Internally for Stable Unity Gain
Operation
• Direct Replacement for ICL7650
• Available in 8-Pin Plastic DIP and 14-Pin Plastic
DIP Packages
Applications
• Instrumentation
• Medical Instrumentation
• Embedded Control
• Temperature Sensor Amplifier
• Strain Gage Amplifier
Device Selection Table
Part
Number
Package
Temperature
Range
Max VOS
TC7650CPA 8-Pin PDIP 0°C to +70°C
TC7650CPD 14-Pin PDIP 0°C to +70°C
5µV
5µV
Package Type
8-Pin DIP
CA 1
8 CB
–INPUT 2
7 VDD
+INPUT 3 TC7650CPA 6 OUTPUT
VSS 4
5 OUTPUT CLAMP
14-Pin DIP
CB 1
CA 2
14 INT/EXT
13 EXT CLK IN
NC 3
12 INT CLK OUT
–INPUT 4 TC7650CPD 11 VDD
+INPUT 5
10 OUTPUT
NC 6
VSS 7
9 OUTPUT CLAMP
8 CRETN
NC = NO INTERNAL CONNECTION
© 2002 Microchip Technology Inc.
DS21463B-page 1
1 page  
TC7650
tion region, where the main amplifier takes over from
the null amplifier. The clock frequency sets the transi-
tion region.
3.3 Intermodulation
Previous chopper stabilized amplifiers have suffered
from intermodulation effects between the chopper fre-
quency and input signals. These arise because the
finite AC gain of the amplifier results in a small AC sig-
nal at the input. This is seen by the zeroing circuit as an
error signal, which is chopped and fed back, thus inject-
ing sum and difference frequencies, and causing dis-
turbances to the gain and phase versus frequency
characteristics near the chopping frequency. These
effects are substantially reduced in the TC7650 by
feeding the nulling circuit with a dynamic current corre-
sponding to the compensation capacitor current in such
a way as to cancel that portion of the input signal due
to a finite AC gain. The intermodulation and gain/phase
disturbances are held to very low values, and can gen-
erally be ignored.
FIGURE 3-1:
TC7650 CONTAINS A NULLING AND MAIN AMPLIFIER. OFFSET CORRECTION
VOLTAGES ARE STORED ON TWO EXTERNAL CAPACITORS.
V+
Analog Input
V-
B
TC7650
Main
+ Amplifier
Null
-
Gain = AM
VOUT
+B
A Null
-
A
Null
Amplifier
CB
CA
Gain = AN , Offset = VOSN
FIGURE 3-2:
VDD VSS
NULLING CAPACITOR
CONNECTION
VDD
4 - 11
7
TC7650
10
5+
1
8
2
2- 7
6
TC7650
3+
8 CB
1
4
VSS
CA CB
14-PIN PACKAGE
CA
8-PIN PACKAGE
3.4 Nulling Capacitor Connection
The offset voltage correction capacitors are connected
to CA and CB. The common capacitor connection is
made to VSS (Pin 4) on the 8-pin packages and to
capacitor return (CRETN, Pin 8) on the 14-pin packages.
The common connection should be made through a
separate PC trace or wire to avoid voltage drops. The
capacitors outside foil, if possible, should be connected
to CRETN or VSS.
3.5 Clock Operation
The internal oscillator is set for a 200Hz nominal chop-
ping frequency on both the 8- and 14-pin DIPs. With the
14-pin DIP TC7650, the 200 Hz internal chopping fre-
quency is available at the internal clock output (Pin 12).
A 400Hz nominal signal will be present at the external
clock input pin (Pin 13) with INT/EXT high or open. This
is the internal clock signal before a divide-by-two oper-
ation.
The 14-pin DIP device can be driven by an external
clock. The INT/EXT input (Pin 14) has an internal pull-
up and may be left open for internal clock operation. If
an external clock is used, INT/EXT must be tied to VSS
(Pin 7) to disable the internal clock. The external clock
signal is applied to the external clock input (Pin 13).
The external clock amplitude should swing between
VDD and ground for power supplies up to ±6V and
between V+ and V+ -6V for higher supply voltages.
At low frequencies the external clock duty cycle is not
critical, since an internal divide-by-two gives the
desired 50% switching duty cycle. The offset storage
correction capacitors are charged only when the exter-
nal clock input is high. A 50% to 80% external clock
© 2002 Microchip Technology Inc.
DS21463B-page 5
5 Page 
TC7650
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences
and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of
the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
© 2002 Microchip Technology Inc.
DS21463B-page 11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet TC7650CPA.PDF ] | |
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