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PDF TC74VHCT138AF Data sheet ( Hoja de datos )

Número de pieza TC74VHCT138AF
Descripción 3-TO-8 LINE DECODER
Fabricantes Toshiba 
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TC74VHCT138AF/AFN/AFT/AFK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHCT138AF,TC74VHCT138AFN,TC74VHCT138AFT,TC74VHCT138AFK
3-to-8 Line Decoder
The TC74VHCT138 is an advanced high speed CMOS 3-to-8
LINE DECODER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power
dissipation.
When the device is enabled, 3 Binary Select inputs (A, B and
C) determine which one of the outputs ( Y0 - Y7 ) will go low.
When enable input G1 is held low or either G2A or G2B is
held high, decoding function is inhibited and all outputs go high.
G1, G2A , and G2B inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.3
V to 5 V system.
Input protection and output circuit ensure that 0 to 5.5 V can
be applied to the input and output (Note) pins without regard to
the supply voltage. These structure prevents device destruction
due to mismatched supply and input/output voltages such as
battery back up, hot board insertion, etc.
Note: VCC = 0 V
Features
High speed: tpd = 7.6 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
Compatible with TTL outputs: VIL = 0.8 V (max)
VIH = 2.0 V (min)
Power down protection is provided on all inputs and outputs
Balanced propagation delays: tpLH ∼− tpHL
Pin and function compatible with the 74 series
(74AC/HC/F/ALS/LS etc.) 138 type.
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74VHCT138AF
TC74VHCT138AFN
TC74VHCT138AFT
TC74VHCT138AFK
Weight
SOP16-P-300-1.27A
SOL16-P-150-1.27
TSSOP16-P-0044-0.65A
VSSOP16-P-0030-0.50
: 0.18 g (typ.)
: 0.13 g (typ.)
: 0.06 g (typ.)
: 0.02 g (typ.)
1 2007-10-01

1 page




TC74VHCT138AF pdf
TC74VHCT138AF/AFN/AFT/AFK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(A, B, C- Y )
Propagation delay
time
(G1- Y )
Propagation delay
time
( G2 - Y )
Input capacitance
Power dissipation
capacitance
Symbol
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
CIN
CPD
Test Condition
VCC (V) CL (pF)
15
5.0 ± 0.5
50
Ta = 25°C
Min Typ. Max
7.6 10.4
8.1 11.4
15 6.6 9.1
5.0 ± 0.5
50 7.1 10.1
15 7.0 9.6
5.0 ± 0.5
50 7.5 10.6
⎯ ⎯ 4 10
(Note) 49
Ta = −40 to
85°C
Min Max
1.0 12.0
1.0 13.0
1.0 10.5
1.0 11.5
1.0 11.0
1.0 12.0
10
⎯⎯
Unit
ns
ns
ns
pF
pF
Note:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC
5 2007-10-01

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