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Toshiba - OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT

Numéro de référence TC74VHC573F
Description OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT
Fabricant Toshiba 
Logo Toshiba 





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TC74VHC573F fiche technique
TC74VHC573F/FW/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC573F,TC74VHC573FW,TC74VHC573FT,TC74VHC573FK
Octal D-Type Latch with 3-State Output
The TC74VHC573 is an advanced high speed CMOS OCTAL
LATCH with 3-STATE OUTPUT fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This 8-bit D-type latch is controlled by a latch enable input
(LE) and a output enable input ( OE ).
When the OE input is high, the eight outputs are in a high
impedance state.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
High speed: tpd = 4.5 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 µA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2 to 5.5 V
Low noise: VOLP = 1.2 V (max)
Pin and function compatible with 74ALS573
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74VHC573F
TC74VHC573FW
TC74VHC573FT
Weight
SOP20-P-300-1.27A
: 0.22 g (typ.)
SOP20-P-300-1.27
: 0.22 g (typ.)
SOL20-P-300-1.27
: 0.46 g (typ.)
TSSOP20-P-0044-0.65A : 0.08 g (typ.)
VSSOP20-P-0030-0.50 : 0.03 g (typ.)
TC74VHC573FK
1 2006-02-01

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TC74VHC573F OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT Toshiba
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TC74VHC573FK OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT Toshiba
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TC74VHC573FT OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT Toshiba
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