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PDF 74LS374 Data sheet ( Hoja de datos )

Número de pieza 74LS374
Descripción LOW POWER SCHOTTKY
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



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No Preview Available ! 74LS374 Hoja de datos, Descripción, Manual

SN74LS373 SN74LS374
Octal Transparent Latch
with 3-State Outputs;
Octal D-Type Flip-Flop
with 3-State Output
The SN74LS373 consists of eight latches with 3-state outputs for
bus organized system applications. The flip-flops appear transparent
to the data (data changes asynchronously) when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH the bus output is in the high impedance state.
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop
featuring separate D-type inputs for each flip-flop and 3-state outputs
for bus oriented applications. A buffered Clock (CP) and Output
Enable (OE) is common to all flip-flops. The SN74LS374 is
manufactured using advanced Low Power Schottky technology and is
compatible with all ON Semiconductor TTL families.
Eight Latches in a Single Package
3-State Outputs for Bus Interfacing
Hysteresis on Latch Enable
Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
Hysteresis on Clock Input to Improve Noise Margin
Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
– 2.6
24
mA
mA
http://onsemi.com
LOW
POWER
SCHOTTKY
20
1
PLASTIC
N SUFFIX
CASE 738
20
1
SOIC
DW SUFFIX
CASE 751D
ORDERING INFORMATION
Device
Package
Shipping
SN74LS373N 16 Pin DIP 1440 Units/Box
SN74LS373DW 16 Pin
2500/Tape & Reel
SN74LS374N 16 Pin DIP 1440 Units/Box
SN74LS374DW 16 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Publication Order Number:
SN74LS373/D

1 page




74LS374 pdf
SN74LS373 SN74LS374
SN74LS373
AC WAVEFORMS
LE
Dn
OUTPUT
tW
1.3 V
ts
tW
th
tPLH tPHL
Figure 1.
OE
tPZL
VOUT
1.3 V
1.3 V
Figure 2.
1.3 V
0.5 V
tPLZ
1.3 V
VOL
OE
tPZH
VOUT
1.3 V
tPHZ
1.3 V
Figure 3.
1.3 V
VOH
1.3 V
0.5 V
TO OUTPUT
UNDER TEST
VCC
RL
SW1
AC LOAD CIRCUIT
5.0 k
CL* SW2
SWITCH POSITIONS
SYMBOL
tPZH
tPZL
tPLZ
tPHZ
SW1
Open
Closed
Closed
Closed
SW2
Closed
Open
Closed
Closed
* Includes Jig and Probe Capacitance.
Figure 4.
http://onsemi.com
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