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PDF 74LS293 Data sheet ( Hoja de datos )
| Número de pieza | 74LS293 | |
| Descripción | DECADE COUNTER; 4-BIT BINARY COUNTER | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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DECADE COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS290 and SN54/ 74LS293 are high-speed 4-bit ripple type
counters partitioned into two sections. Each counter has a divide-by-two sec-
tion and either a divide-by-five (LS290) or divide-by-eight (LS293) section
which are triggered by a HIGH-to-LOW transition on the clock inputs. Each
section can be used separately or tied together (Q to CP)to form BCD,
Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated
Master Reset (Clear), and the LS290 also has a 2-input gated Master Set
(Preset 9).
• Corner Power Pin Versions of the LS90 and LS93
• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, Bi-Quinary, Binary
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC MR MR CP1 CP0 Q0 Q3
14 13 12 11 10 9
8
LS290
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1234567
MS NC MS Q2 Q1 NC GND
VCC MR
14 13
MR CP1 CP0
12 11 10
Q0
9
Q3
8
LS293
SN54/74LS290
SN54/74LS293
DECADE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
14
1
N SUFFIX
PLASTIC
CASE 646-06
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
1234567
NC NC NC Q2 Q1 NC GND
PIN NAMES
LOADING (Note a)
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
Clock (Active LOW going edge) Input to ÷ 2 Section.
Clock (Active LOW going edge) Input to ÷ 5 Section (LS290).
Clock (Active LOW going edge) Input to ÷ 8 Section (LS293).
Master Reset (Clear) Inputs
Master Set (Preset-9, LS290) Inputs
Output from ÷ 2 Section (Notes b & c)
Outputs from ÷ 5 & ÷ 8 Sections (Note b)
HIGH
0.05 U.L.
0.05 U.L.
0.05 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
LOW
1.5 U.L.
2.0 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
c) The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 Input of the device.
FAST AND LS TTL DATA
5-466
1 page  
SN54/74LS290 D SN54/74LS293
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF)
Symbol
fMAX
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
tPHL
Parameter
CP0 Input Clock Frequency
CP1 Input Clock Frequency
Propagation Delay,
CP0 Input to Q0 Output
CP0 Input to Q3 Output
CP1 Input to Q1 Output
CP1 Input to Q2 Output
CP1 Input to Q3 Output
MS Input to Q0 and Q3 Outputs
MS Input to Q1 and Q2 Outputs
MR Input to Any Output
Min
32
16
LS290
Typ
10
12
32
34
10
14
21
23
21
23
20
26
26
Limits
Max Min
32
16
16
18
48
50
16
21
32
35
32
35
30
40
40
LS293
Typ
10
12
46
46
10
14
21
23
34
34
26
Max
16
18
70
70
16
21
32
35
51
51
40
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
LS290
LS293
Symbol
Parameter
Min Max Min Max
Unit
tW CP0 Pulse Width
15 15
ns
tW CP1 Pulse Width
30 30
ns
tW MS Pulse Width
15 ns
tW MR Pulse Width
15 15
ns
trec Recovery Time MR to CP
25 25
ns
RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition form HIGH-to-LOW in order to
recognize and transfer HIGH data to the Q outputs.
AC WAVEFORMS
*CP 1.3 V
tPHL
Q 1.3 V
1.3 V
tW tPLH
1.3 V
Figure 1
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.
MR & MS
1.3 V
CP
tPHL
Q
1.3 V
tW trec
1.3 V
1.3 V
MS 1.3 V
CP
Q0 ⋅ Q3
(LS290)
tPLH
1.3 V
tW trec
1.3 V
1.3 V
Figure 2
Figure 3
FAST AND LS TTL DATA
5-470
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| PDF Descargar | [ Datasheet 74LS293.PDF ] | |
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