74HCT4052 Datasheet PDF - Philips
| Part Number | 74HCT4052 | |
| Description | Dual 4-channel analog multiplexer/demultiplexer | |
| Manufacturers | Philips | |
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74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Rev. 11 — 10 February 2016
Product data sheet
1. General description
The 74HC4052; 74HCT4052 is a dual single-pole quad-throw analog switch (2x SP4T)
suitable for use in analog or digital 4:1 multiplexer/demultiplexer applications. Each switch
features four independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common
input/output (nZ). A digital enable input (E) and two digital select inputs (S0 and S1) are
common to both switches. When E is HIGH, the switches are turned off. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to
voltages in excess of VCC.
2. Features and benefits
Wide analog input voltage range from 5 V to +5 V
Low ON resistance:
80 (typical) at VCC VEE = 4.5 V
70 (typical) at VCC VEE = 6.0 V
60 (typical) at VCC VEE = 9.0 V
Logic level translation: to enable 5 V logic to communicate with 5 V analog signals
Typical ‘break before make’ built-in
Complies with JEDEC standard no. 7A
Input levels:
For 74HC4052: CMOS level
For 74HCT4052: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
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NXP Semiconductors
74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
7. Functional description
7.1 Function table
Table 3.
Input
E
L
L
L
L
H
Function table[1]
S1
L
L
H
H
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
S0
L
H
L
H
X
8. Limiting values
Channel on
nY0 and nZ
nY1 and nZ
nY2 and nZ
nY3 and nZ
none
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to VEE = GND (ground = 0 V).
Symbol Parameter
Conditions
VCC
IIK
ISK
ISW
IEE
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
switch clamping current
switch current
supply current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VSW < 0.5 V or VSW > VCC + 0.5 V
0.5 V < VSW < VCC + 0.5 V
SO16, (T)SSOP16, and DHVQFN16
package
P power dissipation
per switch
Min
[1] 0.5
-
-
-
-
-
-
65
[2] -
-
Max
+11.0
20
20
25
20
50
50
+150
500
Unit
V
mA
mA
mA
mA
mA
mA
C
mW
100 mW
[1] To avoid drawing VCC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must
not exceed 0.4 V. If the switch current flows into pins nZ, no VCC current will flow out of pins nYn. In this case there is no limit for the
voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed VCC or VEE.
[2] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
74HC_HCT4052
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 10 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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