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PDF 74HCT2G00DP Data sheet ( Hoja de datos )
| Número de pieza | 74HCT2G00DP | |
| Descripción | Dual 2-input NAND gate | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
74HC2G00; 74HCT2G00
Dual 2-input NAND gate
Product specification
Supersedes data of 2002 Jul 10
2003 Feb 12
1 page  
Philips Semiconductors
Dual 2-input NAND gate
Product specification
74HC2G00; 74HCT2G00
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VI
VO
Tamb
supply voltage
input voltage
output voltage
operating ambient
temperature
tr, tf input rise and fall times
CONDITIONS
74HC2G00
74HCT2G00
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
2.0 5.0 6.0 4.5 5.0 5.5 V
0 − VCC 0 − VCC V
0 − VCC 0 − VCC V
see DC and AC −40 +25 +125 −40 +25 +125 °C
characteristics per
device
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
− − 1000 − − − ns
− 6.0 500 − 6.0 500 ns
− − 400 − − − ns
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
VCC supply voltage
IIK input diode current
IOK output diode current
IO output source or sink current
ICC VCC or GND current
Tstg storage temperature
PD power dissipation per package
CONDITIONS
VI < −0.5 V or VI > VCC + 0.5 V; note 1
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−0.5 V < VO < VCC + 0.5 V; note 1
note 1
for temperature range from −40 to +125 °C;
note 2
MIN.
−0.5
−
−
−
−
−65
−
MAX. UNIT
+7.0 V
±20 mA
±20 mA
25 mA
50
+150
300
mA
°C
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 110 °C the value of PD derates linearly with 8 mW/K.
2003 Feb 12
5
5 Page 
Philips Semiconductors
Dual 2-input NAND gate
Product specification
74HC2G00; 74HCT2G00
PACKAGE OUTLINES
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
D
y
Z
8
5
c
E AX
HE v M A
pin 1 index
1
e
4
bp w M
A A2
A1
(A3)
detail X
Lp
L
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
D(1)
3.1
2.9
E(1) e
3.1
2.9
0.65
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
HE
4.1
3.9
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT505-2
---
L Lp v w y Z(1)
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
θ
8°
0°
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
2003 Feb 12
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 74HCT2G00DP.PDF ] | |
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