PDF C5002 Data sheet ( Hoja de datos )

Número de pieza	C5002
Descripción	Low Skew Muliple Frequency PCI Clock Generator with EMI Reducing SSCG
Fabricantes	International
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C5002 Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG Approved Product Product Features § Produces PCI output clocks that are individually selectable for 33.3 or 66.6 MHz under SMBus or strapping control. § Separate output buffer power supply for reduced noise, crosstalk and jitter. § input clock frequency standard 14.31818 MHz § Output clocks frequency individually selectable via SMBus or hardware bi-directional pin strapping. § SSCG EMI reduction at 1.0% width § Individual clock disables via SMBus control § All output clocks skewed within a 500 pS window § Cycle to Cycle jitter ± 250 pS § Output duty cycle is automatically 50% (±10%) adjusted § Clock feed through mode and OE pins for logic testing § Glitchless clock enabling and disabling transitions § 28-pin TSSOP or SSOP package Block Diagram XIN XOUT Reference Oscillator ÷1 ÷2 ÷1 ÷2 M U REF- X CLK0/S0 CLK1/S PLL ÷1 ÷2 ÷1 ÷2 CLK2/S 2 CLK3/S3 ÷1 ÷2 CLK4/S4 ÷1 ÷2 CLK5/S5 ÷1 ÷2 CLK6/S6 ÷1 ÷2 CLK7/S7 ÷1 ÷2 CLK8/S8 OE SDATA SCLK SMBus LOGIC ÷1 ÷2 ÷4, ÷8 CLK9/S9 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Output Enable Logic Functionality Table OE CLK(0:9) PLL 1 (HIGH) Enabled Running 0 (LOW) Tri State Stopped* See Output Enable Control section of this datasheet. Pin Configuration VDD XIN XOUT VSS OE SCLK SDATA VSS VSS CLK9/S9 CLK8/S8 VDD5 VSS CLK7/S7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 VDD1 27 REF-CLK0/S0 26 CLK1/S1 25 VSS 24 VDD2 23 CLK2/S2 22 CLK3/S3 21 VSS 20 VDD3 19 CLK4/S4 18 CLK5/S5 17 VSS 16. VDD4 15 CLK6/S6 Document#: 38-07014 Rev. * 5/4/2001 Page 1 of 16 1 page C5002 Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG Approved Product Output Enable Control The Output Enable Pin (pin 5) on this device serves two (2) purposes. The primary function is to force all clock outputs to a tri-state electrical mode. This is done to support automated testing of fabricated PCB assemblies. The second function of this pin is to bring the internal circuitry of the device to a lower power mode when the pin is driven to a logic low level. In this mode, all unneeded circuitry (e.g., the PLL, counters and clock control logic) have their power removed. Designers who use this functionality should pay close attention to the TOEL characteristic listed in the AC Parameters section of this datasheet. This function is particularly useful in mobil designs where power savings is a crucial design factor. Data stored in the SMBus registers is maintained during OE active periods. Application Note for Selection on BI-DIRECTIONAL Pins Pins 10, 11, 14, 15, 18, 19, 22, 23, 26 and 27 are Power up bi-directional pins and are used for selecting power up output frequencies of this devices output clocks (see Pin description, Page 2). During power-up of the device, these pins are in input mode, therefore, they are considered input select pins internal to the IC, these pins have a large value pull-up each (250KΩ), therefore, a selection “1” is the default and will select a 66 MHz output frequency. If the system uses a slow power supply (over 5 ms settling time), then it is recommended to use an external pull-up (Rup) in order to insure a high selection. In this case, the designer may choose one of two configurations, see FIG. 3A and Fig. 3B. Fig. 3A represents an additional pull up resistor 50KΩ connected from the pin to the power line, which allows a faster pull to a high level. If a selection “0” is desired, then a jumper is placed on JP1 to a 5KΩ resistor as implemented as shown in Fig. 3A. Please note the selection resistors (Rup and Rdn) are placed before the Damping resistor (Rd) close to the pin. C5002 Bidirectional Vdd Rup 50K Rd Load JP1 JUMPER Rdn 5K Fig. 3A Vdd JP2 3 Way Jumper Fig. 3B represents a single resistor 10KΩ connected to a 3-way jumper, JP2. When a “1” selection is desired, a jumper is placed between leads 1 and 3. When a “0” selection is desired, a jumper is placed between leads 1 and 2. If the system power supply is fast (less than 5 mSec settling time), then FIG 3A only applies and Pull up Rup resistor is not necessary. C5002 Bidirectional Rsel 10K Rd Load Fig. 3B The electrical length of the trace that connects the selection resistor to the devices pin should be kept as short as possible. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07014 Rev. 5/4/2001 Page 5 of 16 5 Page C5002 Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG Approved Product Crystal and Reference Oscillator Parameters Characteristic Symbol Min Typ Max Units Conditions Frequency Fo 12.00 14.31818 16.00 MHz Tolerance TC - - +/-100 PPM Calibration Note 1 TS - - +/- 100 PPM Stability (Ta -10 to +60C) Note 1 TA - - 5 PPM Aging (first year @ 25C) Note 1 Mode OM - - - Parallel Resonant Pin Capacitance CP 32 pF Capacitance of XIN and Xout pins to ground (each) DC Bias Voltage VBIAS 0.3Vdd Vdd/2 0.7Vdd V Startup time Ts - - 30 µS Load Capacitance CL - 16 - pF See calculation section below Effective Series resistance (ESR) R1 - - 40 Ohms Power Dissipation DL - - 0.10 mW Note 1 Shunt Capacitance CO - -- 8 pF Crystal’s internal package capacitance (total) For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. Budgeting Calculations Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore = 2.0 pF Clock generator internal pin capacitance of 32 pF, Load to the crystal is therefore = 16.0 pF The total capacitance see by the crystal would therefore be = 18.0 pF. Note 1: It is recommended but not mandatory that a crystal meets these specifications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07014 Rev. 5/04/2001 Page 11 of 16 11 Page

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