IDT74FCT273APB Datasheet PDF - Integrated Device Tech
| Part Number | IDT74FCT273APB | |
| Description | FAST CMOS OCTAL FLIP-FLOP WITH MASTER RESET | |
| Manufacturers | Integrated Device Tech | |
| Logo |  |
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®
Integrated Device Technology, Inc.
FAST CMOS
OCTAL FLIP-FLOP
WITH MASTER RESET
IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C
FEATURES:
• IDT54/74FCT273 equivalent to FAST™ speed;
• IDT54/74FCT273A 45% faster than FAST
• IDT54/74FCT273C 55% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST
(5µA max.)
• Octal D flip-flop with Master Reset
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT273/A/C are octal D flip-flops built using
an advanced dual metal CMOS technology. The IDT54/
74FCT273/A/C have eight edge-triggered D-type flip-flops
MRwith individual D inputs and O outputs. The common buffered
Clock (CP) and Master Reset ( ) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.
All outputs will be forced LOW independently of Clock or
MRData inputs by a LOW voltage level on the input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
CP
DQ
CP
RD
DQ
CP
RD
MR
O0 O1
PIN CONFIGURATIONS
DQ
CP
RD
O2
DQ
CP
RD
O3
DQ
CP
RD
O4
DQ
CP
RD
O5
DQ
CP
RD
O6
DQ
CP
RD
O7
2558 drw 01
MR
O0
D0
D1
O1
O2
D2
D3
O3
GND
1 20
2 19
3 18
4 P20-1 17
5
D20-1
SO20-2
16
6 & 15
7 E20-1 14
8 13
9 12
10 11
Vcc
O7
D7
D6
O6
O5
D5
D4
O4
CP
DIP/SOIC/CERPACK
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
7.10
INDEX
3 2 20 19
D1 4
1 18 D7
O1 5
17 D6
O2 6 L20-2 16 O6
D2 7
15 O5
D3 8
14 D5
9 10 11 12 13
LCC
TOP VIEW
2558 drw 02
MAY 1992
DSC-4609/2
1
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IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C
Symbol
tPLH
tPHL
Parameter
Propagation Delay
Clock to Output
Condition(1)
CL = 50 pF
RL = 500Ω
Com’l.
Mil.
Com’l.
Mil.
Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3
Com’l.
Mil.
Min.(2) Max. Min.(2) Max.
2.0 5.8 2.0 6.5
Unit
ns
MRtPHL Propagation Delay
to Output
2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3 2.0 6.1 2.0 6.8 ns
tSU Set-up Time HIGH
or LOW Data to CP
3.0 — 3.5 — 2.0 — 2.0 — 2.0 — 2.0 — ns
tH Hold Time HIGH
or LOW Data to CP
2.0 — 2.0 — 1.5 — 1.5 — 1.5 — 1.5 — ns
tW Clock Pulse Width
HIGH or LOW
MRtW Pulse Width
LOW
7.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns
7.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns
MRtREM
Recovery Time
to CP
4.0 — 5.0 — 2.0 — 2.5 — 2.0 — 2.5 — ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2558 tbl 07
7.10 5
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| Information | Total 7 Pages | |
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