IDT74FCT161TPB Datasheet PDF - Integrated Device Tech
| Part Number | IDT74FCT161TPB | |
| Description | FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS | |
| Manufacturers | Integrated Device Tech | |
| Logo |  |
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Integrated Device Technology, Inc.
FAST CMOS
SYNCHRONOUS
PRESETTABLE
BINARY COUNTERS
IDT54/74FCT161T/AT/CT
IDT54/74FCT163T/AT/CT
FEATURES:
• Std., A and C speed grades
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
DESCRIPTION:
The IDT54/74FCT161T/163T, IDT54/74FCT161AT/ 163AT
and IDT54/74FCT161CT/163CT are high-speed synchro-
nous modulo-16 binary counters built using an advanced dual
metal CMOS technology. They are synchronously preset-
table for application in programmable dividers and have two
types of count enable inputs plus a terminal count output for
versatility in forming synchronous multi-stage counters. The
IDT54/74FCT161T/AT/CT have asynchronous Master Reset
inputs that override all other inputs and force the outputs LOW.
The IDT54/74FCT163T/AT/CT have Synchronous Reset in-
puts that override counting and parallel loading and allow the
outputs to be simultaneously reset on the rising edge of the
clock.
FUNCTIONAL BLOCK DIAGRAMS
PE
'161 '163
CEP
CET
163
ONLY
P0
P1 P2
P3
TC
CP
MR ('161)
SR ('163)
161
CP ONLY
CP
D CP D
CD
QQ
Q0
Q0
DETAIL A
Q0
DETAIL
A
Q1
DETAIL
A
Q2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
6.7
DETAIL
A
Q3
2611 drw 01
OCTOBER 1994
DSC-4219/4
1
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IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT161T
IDT54/74FCT161AT
IDT54/74FCT161CT
IDT54/74FCT163T
IDT54/74FCT163AT
IDT54/74FCT163CT
Symbol Parameter
Com'l.
Mil. Com'l.
Mil. Com'l
Mil.
Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 2.0 11.0 2.0 11.5 2.0 7.2 2.0 7.5 2.0 5.8 2.0 6.3 ns
tPHL CP to Qn
RL = 500Ω
(PE Input HIGH)
tPLH Propagation Delay
tPHL CP to Qn
(PE Input LOW)
2.0 9.5 2.0 10.0 2.0 6.2 2.0 6.5 2.0 5.8 2.0 6.3 ns
tPLH Propagation Delay
tPHL CP to TC
2.0 15.0 2.0 16.5 2.0 9.8 2.0 10.8 2.0 7.4 2.0 8.3 ns
tPLH Propagation Delay
tPHL CET to TC
1.5 8.5 1.5 9.0 1.5 5.5 1.5 5.9 1.5 5.2 1.5 5.6 ns
tPHL Propagation Delay
MR to Qn ('161)
2.0 13.0 2.0 14.0 2.0 8.5 2.0 9.1 2.0 6.0 2.0 6.6 ns
tPHL Propagation Delay
MR to TC ('161)
2.0 11.5 2.0 12.5 2.0 7.5 2.0 8.2 2.0 7.0 2.0 7.7 ns
tSU Set-up Time,
HIGH or LOW
Pn to CP
tH Hold Time,
HIGH or LOW
Pn to CP
5.0 — 5.5 — 4.0 — 4.5 — 4.0 — 4.5 — ns
1.5 — 2.0 — 1.5 — 2.0 — 1.5 — 2.0 — ns
tSU Set-up Time,
HIGH or LOW
PE or SR to CP
tH Hold Time,
HIGH or LOW
PE or SR to CP
tSU Set-up Time,
HIGH or LOW
CEP or CET to CP
tH Hold Time,
HIGH or LOW
CEP or CET to CP
tW Clock Pulse
Width (Load)
HIGH or LOW
tW Clock Pulse
Width (Count)
HIGH or LOW
tW MR Pulse Width,
LOW ('161)
11.5 — 13.5 — 9.5 — 11.5 — 9.5 — 11.5 — ns
1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
11.5 — 13.0 — 9.5 — 11.0 — 9.5 — 11.0 — ns
0 — 0 — 0 — 0 — 0 — 0 — ns
5.0 — 5.0 — 4.0(3) — 4.0(3) — 4.0(3) — 4.0(3) — ns
7.0 — 8.0 — 6.0 — 7.0 — 6.0 — 7.0 — ns
5.0 — 5.0 — 4.0(3) — 4.0(3) — 4.0(3) — 4.0(3) — ns
tREM
Recovery Time
MR to CP ('161)
6.0 — 6.0 — 5.0 — 5.0 — 5.0 — 5.0 — ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
2611 tbl 07
6.7 5
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