PDF IDT74ALVC244PY Data sheet ( Hoja de datos )

Número de pieza	IDT74ALVC244PY
Descripción	3.3V CMOS OCTAL BUFFER/ DRIVER WITH 3-STATE OUTPUTS
Fabricantes	Integrated Device Tech
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No Preview Available ! IDT74ALVC244 3.3V CMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS 3.3V CMOS OCTAL BUFFER/ DRIVER WITH 3-STATE OUTPUTS INDUSTRIALTEMPERATURERANGE IDT74ALVC244 FEATURES: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V • CMOS power levels (0.4µ W typ. static) • Rail-to-Rail output swing for increased noise margin • Available in QSOP, SOIC, SSOP, and TSSOP packages DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for Heavy Loads APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems DESCRIPTION: This octal buffer/driver is built using advanced dual metal CMOS technology. The ALVC244 is organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. The ALVC244 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. FUNCTIONAL BLOCK DIAGRAM 1OE 1 2 1A1 1A2 4 1A3 6 1A4 8 18 1Y1 16 1Y2 14 1Y3 12 1Y4 2OE 19 11 2A1 13 2A2 15 2A3 17 2A4 9 2Y1 7 2Y2 5 2Y3 3 2Y4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE ©1999 Integrated Device Technology, Inc. 1 MARCH 1999 DSC-4774/1 1 page IDT74ALVC244 3.3V CMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIALTEMPERATURERANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VLOAD 6 6 VIH 2.7 2.7 VT 1.5 1.5 VLZ 300 300 VHZ 300 300 CL 50 50 VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF SAME PHASE INPUT TRANSITION OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPLH tPHL tPHL Propagation Delay VIH VT 0V VOH VT VOL VIH VT 0V ALVC Link Pulse(1, 2) Generator VIN VCC VOUT D.U.T. 500Ω VLOAD Open GND RT 500Ω CL ALVC Link Test Circuit for All Outputs CONTROL INPUT ENABLE tPZL DISABLE tPLZ OUTPUT NORMALLY LOW SWITCH CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times ALVC Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open INPUT OUTPUT 1 OUTPUT 2 tPLH1 tPHL1 tSK (x) tSK (x) VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) ALVC Link DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tSU tH tREM tSU tH Set-up, Hold, and Release Times VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V ALVC Link LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tW Pulse Width VT VT ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 5 Page

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