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IDT72V3642 fiches techniques PDF

Integrated Device Tech - 3.3 VOLT CMOS SyncBiFIFO 256 x 36 x 2 512 x 36 x 2 1/024 x 36 x 2

Numéro de référence IDT72V3642
Description 3.3 VOLT CMOS SyncBiFIFO 256 x 36 x 2 512 x 36 x 2 1/024 x 36 x 2
Fabricant Integrated Device Tech 
Logo Integrated Device Tech 





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IDT72V3642 fiche technique
3.3 VOLT CMOS SyncBiFIFOTM
256 x 36 x 2
512 x 36 x 2
1,024 x 36 x 2
IDT72V3622
IDT72V3632
IDT72V3642
.EATURES:
Memory storage capacity:
IDT72V3622 – 256 x 36 x 2
IDT72V3632 – 512 x 36 x 2
IDT72V3642 – 1,024 x 36 x 2
Supports clock frequencies up to 100 MHz
Fast access times of 6.5ns
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Two independent clocked FIFOs buffering data in opposite direc-
tions
Mailbox bypass register for each FIFO
Programmable Almost-Full and Almost-Empty flags
Microprocessor Interface Control Logic
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving
120-pin Thin Quad Flatpack (TQFP)
Functionally compatible to the 5V operating IDT723622/723632/
723642
Industrial temperature range (–40οC to +85οC) is available
DESCRIPTION:
The IDT72V3622/72V3632/72V3642 are functionally compatible versions
of the IDT723622/723632/723642, designed to run off a 3.3V supply for
exceptionally low-power consumption. These devices are monolithic, high-
speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memories which
support clock frequencies up to 100MHz and have read access times as fast
as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on
board each chip buffer data in opposite directions. Communication between
.UNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST1
FIFO1,
Mail1
Reset
Logic
36
Mail 1
Register
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
MBF1
36
FFA/IRA
AFA
FIFO 1
Status Flag
Logic
EFB/ORB
AEB
FS0
FS1
A0 - A35
EFA/ORA
AEA
Programmable Flag Timing
Offset Registers
Mode
10
FIFO 2
Status Flag
Logic
Read
Write
36
Pointer
Pointer
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
MBF2
Mail 2
Register
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FWFT
B0 - B35
FFB/IRB
AFB
36
FIFO2,
Mail2
Reset
Logic
RST2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
4660 drw 01
DECEMBER 2001
DSC-4660/4

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